| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1374 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local 1381 EVT SubVecVT = SubVec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() 1391 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR() 1399 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR() 1420 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, in SplitVecRes_INSERT_SUBVECTOR() 2980 SDValue SubVec = N->getOperand(1); in SplitVecOp_INSERT_SUBVECTOR() local 2985 GetSplitVector(SubVec, Lo, Hi); in SplitVecOp_INSERT_SUBVECTOR() 5797 SDValue SubVec = N->getOperand(1); in WidenVecOp_INSERT_SUBVECTOR() local 5801 SubVec = GetWidenedVector(SubVec); in WidenVecOp_INSERT_SUBVECTOR() 5803 if (SubVec.getValueType().knownBitsLE(VT) && InVec.isUndef() && in WidenVecOp_INSERT_SUBVECTOR() [all …]
|
| H A D | LegalizeIntegerTypes.cpp | 5263 SDValue SubVec = N->getOperand(1); in PromoteIntRes_INSERT_SUBVECTOR() local 5266 EVT SubVecVT = SubVec.getValueType(); in PromoteIntRes_INSERT_SUBVECTOR() 5272 SubVec = DAG.getNode(ISD::ANY_EXTEND, dl, NSubVT, SubVec); in PromoteIntRes_INSERT_SUBVECTOR() 5274 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx); in PromoteIntRes_INSERT_SUBVECTOR()
|
| H A D | DAGCombiner.cpp | 19450 SDValue SubVec = InsertVal.getOperand(0); in combineInsertEltToShuffle() local 19452 EVT SubVecVT = SubVec.getValueType(); in combineInsertEltToShuffle() 19485 ConcatOps[0] = SubVec; in combineInsertEltToShuffle() 22666 for (int SubVec = 0; SubVec != NumSubVecs; ++SubVec) { in visitVECTOR_SHUFFLE() local 22674 NumElts + (SubVec * NumSubElts)); in visitVECTOR_SHUFFLE() 22689 RHS.getOperand(SubVec), in visitVECTOR_SHUFFLE()
|
| H A D | SelectionDAGBuilder.cpp | 7212 SDValue SubVec = getValue(I.getOperand(1)); in visitIntrinsicCall() local 7223 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, in visitIntrinsicCall()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6789 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector() 6799 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector() 6805 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector() 6808 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector() 6816 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector() 6855 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector() 6857 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector() 6866 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector() 6868 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector() 6887 SubVec = DAG.getNode(ISD::OR, dl, WideOpVT, SubVec, Vec); in insert1BitVector() [all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 3483 SDValue SubVec = OpIdx.value(); in LowerOperation() local 3485 if (SubVec.isUndef()) in LowerOperation() 5407 SDValue SubVec = Op.getOperand(1); in lowerINSERT_SUBVECTOR() local 5409 MVT SubVecVT = SubVec.getSimpleValueType(); in lowerINSERT_SUBVECTOR() 5436 SubVec = DAG.getBitcast(SubVecVT, SubVec); in lowerINSERT_SUBVECTOR() 5445 SubVec = DAG.getNode(ISD::ZERO_EXTEND, DL, ExtSubVecVT, SubVec); in lowerINSERT_SUBVECTOR() 5467 DAG.getUNDEF(ContainerVT), SubVec, in lowerINSERT_SUBVECTOR() 5470 SubVec = convertFromScalableVector(VecVT, SubVec, DAG, Subtarget); in lowerINSERT_SUBVECTOR() 5471 return DAG.getBitcast(Op.getValueType(), SubVec); in lowerINSERT_SUBVECTOR() 5540 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT, in lowerINSERT_SUBVECTOR() [all …]
|
| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 2364 Value *SubVec = II->getArgOperand(1); in visitCallInst() local 2368 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); in visitCallInst() 2380 return replaceInstUsesWith(CI, SubVec); in visitCallInst() 2393 Value *WidenShuffle = Builder.CreateShuffleVector(SubVec, WidenMask); in visitCallInst()
|
| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 926 CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec, 929 {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9118 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt, in LowerEXTRACT_SUBVECTOR() 9120 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt, in LowerEXTRACT_SUBVECTOR() 9133 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt, in LowerEXTRACT_SUBVECTOR() 15442 SDValue SubVec = N->getOperand(1); in PerformInsertSubvectorCombine() local 15445 EVT SubVT = SubVec.getValueType(); in PerformInsertSubvectorCombine() 15469 Lo = SubVec; in PerformInsertSubvectorCombine() 15475 Hi = SubVec; in PerformInsertSubvectorCombine() 21437 SubVec, in lowerInterleavedLoad() 21440 SubVecs[SV].push_back(SubVec); in lowerInterleavedLoad() 21449 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local [all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13146 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local 13149 SubVec = Builder.CreateExtractVector( in lowerInterleavedLoad() 13150 FVTy, SubVec, in lowerInterleavedLoad() 13155 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad() 13159 SubVecs[SVI].push_back(SubVec); in lowerInterleavedLoad() 13168 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local 13170 SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0]; in lowerInterleavedLoad() 15372 SDValue SubVec = N->getOperand(1); in performInsertSubvectorCombine() local 15375 EVT SubVT = SubVec.getValueType(); in performInsertSubvectorCombine() 15398 Lo = SubVec; in performInsertSubvectorCombine() [all …]
|
| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | Verifier.cpp | 5575 Value *SubVec = Call.getArgOperand(1); in visitIntrinsicCall() local 5580 VectorType *SubVecTy = cast<VectorType>(SubVec->getType()); in visitIntrinsicCall()
|
| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 6149 Value *SubVec = Call->getArgOperand(1); in simplifyIntrinsic() local 6157 if (match(SubVec, in simplifyIntrinsic()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 5870 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE() local 5873 Pieces.push_back(SubVec); in lowerVECTOR_SHUFFLE()
|