Lines Matching refs:SubVec
6731 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local
6736 if (SubVec.isUndef()) in insert1BitVector()
6757 SubVec, Idx); in insert1BitVector()
6761 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector()
6777 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6779 SubVec, ZeroIdx); in insert1BitVector()
6780 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector()
6784 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6785 Undef, SubVec, ZeroIdx); in insert1BitVector()
6789 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6791 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
6799 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6805 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6808 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
6811 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
6816 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6834 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector()
6855 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6857 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
6859 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector()
6866 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
6868 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
6887 SubVec = DAG.getNode(ISD::OR, dl, WideOpVT, SubVec, Vec); in insert1BitVector()
6890 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
11450 SDValue SubVec = Op.getOperand(i); in LowerAVXCONCAT_VECTORS() local
11451 if (SubVec.isUndef()) in LowerAVXCONCAT_VECTORS()
11453 if (ISD::isBuildVectorAllZeros(SubVec.getNode())) in LowerAVXCONCAT_VECTORS()
11508 SDValue SubVec = Op.getOperand(i); in LowerCONCAT_VECTORSvXi1() local
11509 if (SubVec.isUndef()) in LowerCONCAT_VECTORSvXi1()
11512 if (ISD::isBuildVectorAllZeros(SubVec.getNode())) in LowerCONCAT_VECTORSvXi1()
11529 SDValue SubVec = Op.getOperand(Idx); in LowerCONCAT_VECTORSvXi1() local
11530 unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements(); in LowerCONCAT_VECTORSvXi1()
11531 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ShiftVT, in LowerCONCAT_VECTORSvXi1()
11532 DAG.getUNDEF(ShiftVT), SubVec, in LowerCONCAT_VECTORSvXi1()
11534 Op = DAG.getNode(X86ISD::KSHIFTL, dl, ShiftVT, SubVec, in LowerCONCAT_VECTORSvXi1()
11546 SDValue SubVec = Op.getOperand(Idx); in LowerCONCAT_VECTORSvXi1() local
11547 unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements(); in LowerCONCAT_VECTORSvXi1()
11548 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec, in LowerCONCAT_VECTORSvXi1()
16998 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, in lowerV2X128Shuffle() local
17001 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec, in lowerV2X128Shuffle()
18511 SDValue SubVec = in lowerV4X128Shuffle() local
18514 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec, in lowerV4X128Shuffle()
47832 SDValue SubVec = Src.getOperand(0); in combineScalarAndWithMaskSetcc() local
47833 EVT SubVecVT = SubVec.getValueType(); in combineScalarAndWithMaskSetcc()
47837 if (SubVec.getOpcode() != ISD::SETCC || !TLI.isTypeLegal(SubVecVT) || in combineScalarAndWithMaskSetcc()
47841 EVT SetccVT = SubVec.getOperand(0).getValueType(); in combineScalarAndWithMaskSetcc()
47854 Ops[0] = SubVec; in combineScalarAndWithMaskSetcc()
54195 SDValue SubVec = N->getOperand(1); in combineINSERT_SUBVECTOR() local
54198 MVT SubVecVT = SubVec.getSimpleValueType(); in combineINSERT_SUBVECTOR()
54200 if (Vec.isUndef() && SubVec.isUndef()) in combineINSERT_SUBVECTOR()
54205 (SubVec.isUndef() || ISD::isBuildVectorAllZeros(SubVec.getNode()))) in combineINSERT_SUBVECTOR()
54211 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR && in combineINSERT_SUBVECTOR()
54212 ISD::isBuildVectorAllZeros(SubVec.getOperand(0).getNode())) { in combineINSERT_SUBVECTOR()
54213 uint64_t Idx2Val = SubVec.getConstantOperandVal(2); in combineINSERT_SUBVECTOR()
54216 SubVec.getOperand(1), in combineINSERT_SUBVECTOR()
54224 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 && in combineINSERT_SUBVECTOR()
54225 isNullConstant(SubVec.getOperand(1)) && in combineINSERT_SUBVECTOR()
54226 SubVec.getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR) { in combineINSERT_SUBVECTOR()
54227 SDValue Ins = SubVec.getOperand(0); in combineINSERT_SUBVECTOR()
54244 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && in combineINSERT_SUBVECTOR()
54245 SubVec.getOperand(0).getSimpleValueType() == OpVT && in combineINSERT_SUBVECTOR()
54248 int ExtIdxVal = SubVec.getConstantOperandVal(1); in combineINSERT_SUBVECTOR()
54260 return DAG.getVectorShuffle(OpVT, dl, Vec, SubVec.getOperand(0), Mask); in combineINSERT_SUBVECTOR()
54284 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST) in combineINSERT_SUBVECTOR()
54285 return DAG.getNode(X86ISD::VBROADCAST, dl, OpVT, SubVec.getOperand(0)); in combineINSERT_SUBVECTOR()
54289 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() && in combineINSERT_SUBVECTOR()
54290 SubVec.getOpcode() == X86ISD::VBROADCAST_LOAD) { in combineINSERT_SUBVECTOR()
54291 auto *MemIntr = cast<MemIntrinsicSDNode>(SubVec); in combineINSERT_SUBVECTOR()
54304 if (IdxVal == (OpVT.getVectorNumElements() / 2) && SubVec.hasOneUse() && in combineINSERT_SUBVECTOR()
54305 Vec.getValueSizeInBits() == (2 * SubVec.getValueSizeInBits())) { in combineINSERT_SUBVECTOR()
54307 auto *SubLd = dyn_cast<LoadSDNode>(SubVec); in combineINSERT_SUBVECTOR()
54310 SubVec.getValueSizeInBits() / 8, 0)) in combineINSERT_SUBVECTOR()