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Searched refs:SubReg (Results 1 – 25 of 76) sorted by relevance

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/llvm-project-15.0.7/llvm/test/TableGen/
H A DConcatenatedSubregs.td103 // CHECK-NEXT: SubReg ssub0 = S0
104 // CHECK-NEXT: SubReg ssub1 = S1
108 // CHECK-NEXT: SubReg ssub0 = S9
109 // CHECK-NEXT: SubReg ssub1 = S10
110 // CHECK-NEXT: SubReg ssub2 = S11
111 // CHECK-NEXT: SubReg ssub3 = S12
112 // CHECK-NEXT: SubReg ssub4 = S13
121 // CHECK-NEXT: SubReg ssub0 = S10
122 // CHECK-NEXT: SubReg ssub1 = S11
126 // CHECK-NEXT: SubReg sub0 = D5
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/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp77 for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) { in SetPhysRegUsed() local
78 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
83 else if (COP0RegClass->contains(SubReg)) in SetPhysRegUsed()
86 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()
87 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
88 AFGR64RegClass->contains(SubReg) || in SetPhysRegUsed()
89 MSA128BRegClass->contains(SubReg)) in SetPhysRegUsed()
91 else if (COP2RegClass->contains(SubReg)) in SetPhysRegUsed()
93 else if (COP3RegClass->contains(SubReg)) in SetPhysRegUsed()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveVariables.cpp195 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
201 LastDefReg = SubReg; in FindLastPartialDef()
288 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
337 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
368 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
450 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
457 if (Live.count(SubReg)) in HandlePhysRegDef()
459 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) { in HandlePhysRegDef()
472 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
473 if (!Live.count(SubReg)) in HandlePhysRegDef()
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H A DLiveIntervalCalc.cpp59 unsigned SubReg = MO.getSubReg(); in calculate() local
60 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
61 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
159 unsigned SubReg = MO.getSubReg(); in extendToUses() local
160 if (SubReg != 0) { in extendToUses()
161 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
H A DPeepholeOptimizer.cpp298 addSource(Reg, SubReg); in ValueTrackerResult()
333 return RegSrcs[Idx].SubReg; in getSrcSubReg()
758 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
792 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1074 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1136 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1147 LookupSrc.SubReg = Res.getSrcSubReg(0); in getNewSource()
1258 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in rewriteSource()
1260 if (Def.SubReg) { in rewriteSource()
1976 BaseReg.SubReg) in getNextSourceFromInsertSubreg()
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H A DDetectDeadLanes.cpp171 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
172 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
421 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
444 if (SubReg == 0) in determineInitialUsedLanes()
447 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
454 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
455 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
H A DLiveIntervals.cpp570 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
571 if (SubReg != 0) { in shrinkToUses()
789 unsigned SubReg = MO.getSubReg(); in addKillFlags() local
790 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg) in addKillFlags()
1031 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1032 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1048 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
1049 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1463 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1464 if (SubReg != 0 && LaneMask.any() in findLastUseBefore()
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H A DMachineInstrBundle.cpp203 unsigned SubReg = *SubRegs; in finalizeBundle() local
204 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
205 LocalDefs.push_back(SubReg); in finalizeBundle()
H A DScheduleDAGInstrs.cpp331 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) { in addPhysRegDeps() local
332 if (Uses.contains(*SubReg)) in addPhysRegDeps()
333 Uses.eraseAll(*SubReg); in addPhysRegDeps()
335 Defs.eraseAll(*SubReg); in addPhysRegDeps()
367 unsigned SubReg = MO.getSubReg(); in getLaneMaskForMO() local
368 if (SubReg == 0) in getLaneMaskForMO()
370 return TRI->getSubRegIndexLaneMask(SubReg); in getLaneMaskForMO()
H A DLiveDebugVariables.cpp541 unsigned SubReg; /// Qualifiying subregister for Reg. member
1277 unsigned SubReg = Position.SubReg; in runOnMachineFunction() local
1279 PHIValPos VP = {SI, Reg, SubReg}; in runOnMachineFunction()
1835 unsigned SubReg = It.second.SubReg; in emitDebugValues() local
1841 if (SubReg != 0) in emitDebugValues()
1842 PhysReg = TRI->getSubReg(PhysReg, SubReg); in emitDebugValues()
1854 if (SubReg) in emitDebugValues()
1855 regSizeInBits = TRI->getSubRegIdxSize(SubReg); in emitDebugValues()
1861 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
1876 dbgs() << "DBG_PHI for Vreg " << Reg << " subreg " << SubReg << in emitDebugValues()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp104 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
106 if (SubReg) in isGPR64()
113 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
117 SubReg == 0) || in isFPR64()
119 SubReg == AArch64::dsub); in isFPR64()
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
129 unsigned &SubReg) { in getSrcFromCopy() argument
130 SubReg = 0; in getSrcFromCopy()
138 SubReg = AArch64::dsub; in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
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H A DAArch64RegisterInfo.cpp273 for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i), in UpdateCustomCallPreservedMask() local
275 SubReg.isValid(); ++SubReg) { in UpdateCustomCallPreservedMask()
278 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32); in UpdateCustomCallPreservedMask()
335 for (MCSubRegIterator SubReg(AArch64::ZA, this, /*self=*/true); in getReservedRegs() local
336 SubReg.isValid(); ++SubReg) in getReservedRegs()
337 Reserved.set(*SubReg); in getReservedRegs()
857 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCRegisterInfo.cpp45 MCRegister SubReg) const { in getSubRegIndex()
46 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
51 if (*Subs == SubReg) in getSubRegIndex()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp257 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
351 for (const auto &SubReg : Map) in computeSubRegs() local
353 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second; in computeSubRegs()
358 if (SubReg.second == this) { in computeSubRegs()
372 SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first; in computeSubRegs()
373 if (Ins->second == SubReg.first) in computeSubRegs()
476 const CodeGenRegister *SubReg; in computeSecondarySubRegs() local
552 for (auto SubReg : SubRegs) in computeSuperRegs() local
558 for (auto SubReg : SubRegs) { in computeSuperRegs() local
583 for (auto SubReg : SubRegs) in addSubRegsPreOrder() local
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h303 unsigned SubReg,
352 MachineInstr *findReachingDef(Register Reg, unsigned SubReg,
374 unsigned getChannelFromSubReg(unsigned SubReg) const { in getChannelFromSubReg() argument
375 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0; in getChannelFromSubReg()
379 unsigned getNumChannelsFromSubReg(unsigned SubReg) const { in getNumChannelsFromSubReg() argument
380 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg)); in getNumChannelsFromSubReg()
H A DSIShrinkInstructions.cpp53 Register Reg, unsigned SubReg) const;
55 unsigned SubReg) const;
57 unsigned SubReg) const;
512 unsigned SubReg) const { in instAccessReg()
531 unsigned SubReg) const { in instReadsReg()
532 return instAccessReg(MI->uses(), Reg, SubReg); in instReadsReg()
537 return instAccessReg(MI->defs(), Reg, SubReg); in instModifiesReg()
679 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
680 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
681 .addReg(Y1.Reg, 0, Y1.SubReg) in matchSwap()
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H A DSIPreAllocateWWMRegs.cpp131 const unsigned SubReg = MO.getSubReg(); in rewriteRegs() local
132 if (SubReg != 0) { in rewriteRegs()
133 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
H A DSIRegisterInfo.cpp1483 Register SubReg = e == 1 in buildSpillLoadStore() local
1549 unsigned FinalReg = SubReg; in buildSpillLoadStore()
1690 Register SubReg = in spillSGPR() local
1741 Register SubReg = in spillSGPR() local
1802 Register SubReg = in restoreSGPR() local
1809 SubReg) in restoreSGPR()
1836 Register SubReg = in restoreSGPR() local
1883 Register SubReg = in spillEmergencySGPR() local
1918 Register SubReg = in spillEmergencySGPR() local
1924 SubReg) in spillEmergencySGPR()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h489 unsigned SubReg; member
491 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
492 : Reg(Reg), SubReg(SubReg) {} in Reg()
495 return Reg == P.Reg && SubReg == P.SubReg;
508 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
510 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
2027 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2034 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
H A DMachineInstrBuilder.h98 unsigned SubReg = 0) const {
108 SubReg,
117 unsigned SubReg = 0) const {
118 return addReg(RegNo, Flags | RegState::Define, SubReg);
124 unsigned SubReg = 0) const {
127 return addReg(RegNo, Flags, SubReg);
H A DTargetRegisterInfo.h1038 unsigned SubReg, in shouldCoalesce() argument
1143 unsigned SubReg = 0; variable
1163 unsigned getSubReg() const { return SubReg; } in getSubReg()
1174 SubReg = *Idx++;
1175 if (!SubReg)
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp545 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs() local
546 Reserved.set(SubReg); in getReservedRegs()
552 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs() local
553 Reserved.set(SubReg); in getReservedRegs()
557 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP)) in getReservedRegs() local
558 Reserved.set(SubReg); in getReservedRegs()
571 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs() local
572 Reserved.set(SubReg); in getReservedRegs()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp87 unsigned SubReg; member
98 return (Reg == R.Reg) && (SubReg == R.SubReg); in operator ==()
640 if (DefR.SubReg) { in visitPHI()
1085 if (!R.SubReg) { in getCell()
1937 assert(!DefR.SubReg); in evaluate()
2205 if (!R.SubReg) { in evaluate()
2212 if (R.SubReg != Hexagon::isub_lo && R.SubReg != Hexagon::isub_hi) in evaluate()
2297 if (PR.SubReg) in evaluate()
2994 if (R1.SubReg) { in rewriteHexConstUses()
3061 if (SR.SubReg) { in rewriteHexConstUses()
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/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h55 unsigned SubReg, const TargetRegisterClass *DstRC,
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td38 class GP8<GPR SubReg, string n> : PPCReg<n> {
39 let HWEncoding = SubReg.HWEncoding;
40 let SubRegs = [SubReg];
45 class SPE<GPR SubReg, string n> : PPCReg<n> {
46 let HWEncoding = SubReg.HWEncoding;
47 let SubRegs = [SubReg];
69 class VR<VF SubReg, string n> : PPCReg<n> {
72 let SubRegs = [SubReg];
78 class VSRL<FPR SubReg, string n> : PPCReg<n> {
79 let HWEncoding = SubReg.HWEncoding;
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