1483     Register SubReg = e == 1  in buildSpillLoadStore()  local
1543       SubReg = Register(getSubReg(ValueReg,  in buildSpillLoadStore()
1549     unsigned FinalReg = SubReg;  in buildSpillLoadStore()
1562                            .addReg(SubReg, getKillRegState(IsKill));  in buildSpillLoadStore()
1567       SubReg = TmpIntermediateVGPR;  in buildSpillLoadStore()
1583             .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill));  in buildSpillLoadStore()
1690       Register SubReg =  in spillSGPR()  local
1702                      .addReg(SubReg, getKillRegState(UseKill))  in spillSGPR()
1741         Register SubReg =  in spillSGPR()  local
1749                 .addReg(SubReg, SubKillState)  in spillSGPR()
1802       Register SubReg =  in restoreSGPR()  local
1809                          SubReg)  in restoreSGPR()
1836         Register SubReg =  in restoreSGPR()  local
1843                            SB.TII.get(AMDGPU::V_READLANE_B32), SubReg)  in restoreSGPR()
1883       Register SubReg =  in spillEmergencySGPR()  local
1891               .addReg(SubReg, SubKillState)  in spillEmergencySGPR()
1918       Register SubReg =  in spillEmergencySGPR()  local
1924                          SubReg)  in spillEmergencySGPR()
2834                                     unsigned SubReg,  in shouldCoalesce()  argument
2962 MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg,  in findReachingDef()  argument
2974     LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg)  in findReachingDef()