| /llvm-project-15.0.7/clang/test/SemaTemplate/ |
| H A D | instantiate-subscript.cpp | 8 struct Sub1 { struct
25 template struct Subscript0<Sub1, ConvertibleToInt, long&>;
26 template struct Subscript0<Sub1, Sub0, long&>; // expected-note{{instantiation}}
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| /llvm-project-15.0.7/clang/test/CodeGenObjC/ |
| H A D | objc2-nonfragile-abi-impl.m | 6 @interface Sub1 : Base @end interface
8 @implementation Sub1 @end implementation
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| H A D | category-super-class-meth.m | 8 @interface Sub1 : NSObject @end interface
10 @implementation Sub1 implementation
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| /llvm-project-15.0.7/clang/test/Modules/Inputs/odr_hash-Unresolved/ |
| H A D | module.modulemap | 2 module Sub1 {
3 umbrella "Sub1"
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 244 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm() local
248 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelDAGToDAG.cpp | 210 SDValue Sub1 = in selectInlineAsm() local
214 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in selectInlineAsm()
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| /llvm-project-15.0.7/clang/test/SemaObjC/ |
| H A D | arc-repeated-weak.mm | 333 @interface Sub1 : Base1 interface
335 @interface Sub1(cat) interface in cat
339 void test1(Sub1 *s) {
348 void test2(Sub1 *s) {
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 841 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64() local
846 DL, MVT::i32, LHS, Sub1); in SelectADD_SUB_I64()
851 DL, MVT::i32, RHS, Sub1); in SelectADD_SUB_I64()
884 Sub1, in SelectADD_SUB_I64()
1046 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32); in SelectMUL_LOHI() local
1048 MVT::i32, SDValue(Mad, 0), Sub1); in SelectMUL_LOHI()
1587 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectFlatOffsetImpl() local
1592 DL, MVT::i32, N0, Sub1); in SelectFlatOffsetImpl()
1609 SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1}; in SelectFlatOffsetImpl()
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| H A D | AMDGPUISelLowering.cpp | 1797 SDValue Sub1 = DAG.getBitcast(VT, in LowerUDIVREM64() local
1848 SDValue Rem = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE); in LowerUDIVREM64()
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| H A D | AMDGPULegalizerInfo.cpp | 3579 auto Sub1 = B.buildMerge(S64, {Sub1_Lo, Sub1_Hi}); in legalizeUnsignedDIV_REM64Impl() local
3636 Sel2, Sub1); in legalizeUnsignedDIV_REM64Impl()
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| /llvm-project-15.0.7/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | BasicValueFactory.h | 218 const llvm::APSInt &Sub1(const llvm::APSInt &V) { in Sub1() function
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 434 const MCInst *Sub1 = MI.getOperand(1).getInst(); in EncodeSingleInstruction() local
440 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI); in EncodeSingleInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 466 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
472 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
473 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
478 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
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| H A D | HexagonConstPropagation.cpp | 1951 unsigned Sub1 = MI.getOperand(2).getImm(); in evaluate() local
1956 if (Sub1 != SubLo && Sub1 != SubHi) in evaluate()
1960 assert(Sub1 != Sub2); in evaluate()
1961 bool LoIs1 = (Sub1 == SubLo); in evaluate()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1399 auto compose = [&SubRegAction] (const CodeGenSubRegIndex *Sub1, in computeComposites()
1402 const RegMap &Img1 = SubRegAction.at(Sub1); in computeComposites()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 5823 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm() local
5827 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 9199 SDValue Sub1 = DAG.getNode(ISD::SUB, dl, VT, Quot, in expandFixedPointDiv() local
9203 Sub1, Quot); in expandFixedPointDiv()
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| H A D | DAGCombiner.cpp | 21325 SDValue Sub1 = getSubVectorSrc(Bop1, Index, SubVT); in narrowInsertExtractVectorBinOp() local
21330 if (!Sub0 || !Sub1) in narrowInsertExtractVectorBinOp()
21336 return DAG.getNode(BinOpcode, SDLoc(Extract), SubVT, Sub0, Sub1, in narrowInsertExtractVectorBinOp()
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