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Searched refs:Src2 (Results 1 – 25 of 47) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp536 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UEQ()
546 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UNE()
555 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_ULE()
564 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UGE()
573 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_ULT()
582 IMPLEMENT_UNORDERED(Ty, Src1, Src2) in executeFCMP_UGT()
611 Src2.FloatVal == Src2.FloatVal)); in executeFCMP_ORD()
614 Src2.DoubleVal == Src2.DoubleVal)); in executeFCMP_ORD()
642 Src2.FloatVal != Src2.FloatVal)); in executeFCMP_UNO()
645 Src2.DoubleVal != Src2.DoubleVal)); in executeFCMP_UNO()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp135 const MachineOperand &Src2) const;
208 const MachineOperand &Src2) const { in getMuxOpcode()
209 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
217 if (Src2.isImm() && isInt<8>(Src2.getImm())) in getMuxOpcode()
301 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
303 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock()
319 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
320 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
H A DHexagonPeephole.cpp152 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
156 Register SrcReg = Src2.getReg(); in runOnMachineFunction()
169 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
170 if (Src2.getImm() != 32) in runOnMachineFunction()
H A DHexagonConstPropagation.cpp2602 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg(); in evaluateHexCompare2()
2603 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm(); in evaluateHexCompare2()
2607 RegisterSubReg R2(Src2); in evaluateHexCompare2()
2610 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2616 RegisterSubReg R2(Src2); in evaluateHexCompare2()
2620 APInt A2 = getCmpImm(Opc, 2, Src2); in evaluateHexCompare2()
2634 const MachineOperand &Src2 = MI.getOperand(2); in evaluateHexLogical() local
2646 if (!Src2.isImm()) in evaluateHexLogical()
2648 APInt A(32, Src2.getImm(), true); in evaluateHexLogical()
2657 if (!Src2.isImm()) in evaluateHexLogical()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dprelegalizercombiner-shuffle-vector.mir4 # Check that we canonicalize shuffle_vector(Src1, Src2, mask(0,1,2,3))
5 # into concat_vector(Src1, Src2).
24 # Check that we canonicalize shuffle_vector(Src1, Src2, mask(2,3,0,1,2,3))
25 # into concat_vector(Src2, Src1, Src2).
45 # into concat_vector(Src2, Src1, Src2).
85 # into concat_vector(Src2, undef, Src1).
147 # into concat_vector(Src1, Src2) with bigger vector type.
167 # into concat_vector(Src2, Src1, Src2) with bigger vector type.
187 # into concat_vector(Src2, Src1, Src2) with bigger vector type.
227 # into concat_vector(Src2, undef, Src1) with bigger vector type.
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp358 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma() local
364 if (Src2.isImm() && !TII->isInlineConstant(Src2)) { in shrinkMadFma()
391 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
426 .add(Src2) in shrinkMadFma()
906 const MachineOperand *Src2 = in runOnMachineFunction() local
908 if (!Src2->isReg()) in runOnMachineFunction()
910 Register SReg = Src2->getReg(); in runOnMachineFunction()
934 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction() local
936 if (Src2 && Src2->getReg() != VCCReg) { in runOnMachineFunction()
937 if (Src2->getReg().isVirtual()) in runOnMachineFunction()
[all …]
H A DAMDGPUMacroFusion.cpp46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent() local
48 return FirstMI->definesRegister(Src2->getReg(), TRI); in shouldScheduleAdjacent()
H A DGCNDPPCombine.cpp318 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst() local
319 if (Src2) { in createDPPInst()
321 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
326 DPPInst.add(*Src2); in createDPPInst()
363 assert(Src2 && "Expected vop3p with 3 operands"); in createDPPInst()
653 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov() local
656 (Src2 && Src2->isIdenticalTo(*Src0)))) || in combineDPPMov()
658 (Src2 && Src2->isIdenticalTo(*Src1))))) { in combineDPPMov()
H A DAMDGPUInstCombineIntrinsic.cpp43 const APFloat &Src2) { in fmed3AMDGCN() argument
44 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2); in fmed3AMDGCN()
49 return maxnum(Src1, Src2); in fmed3AMDGCN()
54 return maxnum(Src0, Src2); in fmed3AMDGCN()
656 Value *Src2 = II.getArgOperand(2); in instCombineIntrinsic() local
663 NewCall = IC.Builder.CreateMinNum(Src1, Src2); in instCombineIntrinsic()
665 NewCall = IC.Builder.CreateMinNum(Src0, Src2); in instCombineIntrinsic()
666 } else if (match(Src2, PatternMatch::m_NaN()) || isa<UndefValue>(Src2)) { in instCombineIntrinsic()
685 if (isa<Constant>(Src1) && !isa<Constant>(Src2)) { in instCombineIntrinsic()
686 std::swap(Src1, Src2); in instCombineIntrinsic()
[all …]
H A DSIOptimizeExecMasking.cpp143 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
144 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
159 const MachineOperand &Src2 = MI.getOperand(2); in isLogicalOpOnExec() local
160 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
H A DAMDGPURegBankCombiner.cpp281 MachineInstr *Src2 = getDefIgnoringCopies(MI.getOperand(4).getReg(), MRI); in matchFPMed3ToClamp() local
285 if (isFCst(Src1) && !isFCst(Src2)) in matchFPMed3ToClamp()
286 std::swap(Src1, Src2); in matchFPMed3ToClamp()
289 if (!isClampZeroToOne(Src1, Src2)) in matchFPMed3ToClamp()
H A DSIPeepholeSDWA.cpp621 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in matchSDWAOperand() local
622 auto Width = foldToImm(*Src2); in matchSDWAOperand()
1047 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in convertToSDWA() local
1048 assert(Src2); in convertToSDWA()
1049 SDWAInst.add(*Src2); in convertToSDWA()
H A DSIInstrInfo.cpp2995 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
3037 if (Src2->isReg() && Src2->getReg() == Reg) { in FoldImmediate()
3386 .add(*Src2); in convertToThreeAddress()
3407 .add(*Src2); in convertToThreeAddress()
3442 .add(*Src2) in convertToThreeAddress()
3787 if (Src2) { in canShrink()
3808 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
3880 if (Src2) { in buildShrunkInst()
3883 Inst32.add(*Src2); in buildShrunkInst()
5204 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) { in legalizeOperandsVOP3()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.h39 SDValue Src1, SDValue Src2, SDValue Size,
55 SDValue Src1, SDValue Src2,
H A DSystemZSelectionDAGInfo.cpp174 SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
181 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes); in EmitTargetCodeForMemcmp()
183 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size); in EmitTargetCodeForMemcmp()
226 SDValue Src2, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForStrcmp() argument
230 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1, in EmitTargetCodeForStrcmp()
H A DSystemZISelLowering.cpp4194 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_OP() local
4203 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType()); in lowerATOMIC_LOAD_OP()
4227 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
4231 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
4261 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_SUB() local
4263 SDLoc DL(Src2); in lowerATOMIC_LOAD_SUB()
4274 Src2); in lowerATOMIC_LOAD_SUB()
7865 .add(Src2); in emitAtomicLoadBinary()
7907 Register Src2 = MI.getOperand(3).getReg(); in emitAtomicLoadMinMax() local
7962 .addReg(RotatedOldVal).addReg(Src2); in emitAtomicLoadMinMax()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMIPatternMatch.h652 Src2Ty Src2;
654 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
655 : Src0(Src0), Src1(Src1), Src2(Src2) {}
663 Src2.match(MRI, TmpMI->getOperand(3).getReg()));
672 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
674 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
679 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
681 Src0, Src1, Src2);
H A DMachineIRBuilder.h1043 const SrcOp &Src2, ArrayRef<int> Mask);
1687 const SrcOp &Src1, const SrcOp &Src2,
1689 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1694 const SrcOp &Src1, const SrcOp &Src2,
1696 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp152 MCOperand &Src2, MCOperand &RD, in emitBinary() argument
158 Inst.addOperand(Src2); in emitBinary()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp57 Register Src2 = MI.getOperand(2).getReg(); in matchExtractVecEltPairwiseAdd() local
60 auto Cst = getIConstantVRegValWithLookThrough(Src2, MRI); in matchExtractVecEltPairwiseAdd()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
133 Inst.addOperand(Src2); in EmitBinary()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1000 SDValue Src2 = Node->getOperand(2); in Select() local
1004 if (Src2.getValueType() != XLenVT) in Select()
1007 if (auto *C = dyn_cast<ConstantSDNode>(Src2)) { in Select()
1050 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1059 SDValue Src2 = Node->getOperand(3); in Select() local
1063 if (Src2.getValueType() != XLenVT) in Select()
1066 if (auto *C = dyn_cast<ConstantSDNode>(Src2)) { in Select()
1142 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1162 {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}), in Select()
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/
H A Dmemop-folding-int-arith.ll88 define void @add_i16_mem16(i16 %Arg, i16* %Src1, i16* %Src2, i16* %Dst, i32* %Src32) {
94 %L3 = load i16, i16* %Src2
110 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %L3 = load i16, i16* %Src2
262 define void @sub_i16_mem16(i16 %Arg, i16* %Src1, i16* %Src2, i16* %Dst, i32* %Src32) {
268 %L3 = load i16, i16* %Src2
284 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %L3 = load i16, i16* %Src2
370 define void @mul_i16_mem16(i16 %Arg, i16* %Src1, i16* %Src2, i16* %Dst, i32* %Src32) {
376 %L3 = load i16, i16* %Src2
392 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %L3 = load i16, i16* %Src2
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp116 Register Src0, Src1, Src2; in TEST_F() local
135 m_GMul(m_GAdd(m_Reg(Src0), m_Reg(Src1)), m_Reg(Src2))); in TEST_F()
139 EXPECT_EQ(Src2, Copies[2]); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2199 SDValue Src2 = ShuffleSrc2 ? ShuffleSrc2 : DAG.getUNDEF(VecT); in LowerBUILD_VECTOR() local
2207 if (Src2.getValueType() != VecT) { in LowerBUILD_VECTOR()
2209 Src2.getValueType().getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2212 Src2 = DAG.getBitcast(VecT, Src2); in LowerBUILD_VECTOR()
2229 Result = DAG.getVectorShuffle(VecT, DL, Src1, Src2, MaskRef); in LowerBUILD_VECTOR()

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