2987     MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);  in FoldImmediate()  local
2995       if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))  in FoldImmediate()
3037     if (Src2->isReg() && Src2->getReg() == Reg) {  in FoldImmediate()
3096       Src2->ChangeToImmediate(Imm);  in FoldImmediate()
3333   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);  in convertToThreeAddress()  local
3360     if (!Src0Literal && getFoldableImm(Src2, Imm, &DefMI)) {  in convertToThreeAddress()
3386                   .add(*Src2);  in convertToThreeAddress()
3407                   .add(*Src2);  in convertToThreeAddress()
3442             .add(*Src2)  in convertToThreeAddress()
3785   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);  in canShrink()  local
3787   if (Src2) {  in canShrink()
3808         if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||  in canShrink()
3878   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);  in buildShrunkInst()  local
3880   if (Src2) {  in buildShrunkInst()
3883       Inst32.add(*Src2);  in buildShrunkInst()
3891       copyFlagsToImplicitVCC(*Inst32, *Src2);  in buildShrunkInst()
4359     const MachineOperand &Src2 = MI.getOperand(Src2Idx);  in verifyInstruction()  local
4360     if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {  in verifyInstruction()
4362           !compareMachineOp(Src0, Src2)) {  in verifyInstruction()
5196     MachineOperand &Src2 = MI.getOperand(VOP3Idx[2]);  in legalizeOperandsVOP3()  local
5204     if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {  in legalizeOperandsVOP3()
5207         .add(Src2);  in legalizeOperandsVOP3()
5208       Src2.ChangeToRegister(Reg, false);  in legalizeOperandsVOP3()