| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 522 unsigned SplatBitSize; in selectVSplat() local
525 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, in selectVSplat()
1091 unsigned SplatBitSize; in trySelect() local
1100 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, in trySelect()
1105 switch (SplatBitSize) { in trySelect()
1138 ((ABI.IsO32() && SplatBitSize < 64) || in trySelect()
1145 bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64; in trySelect()
1152 SplatBitSize == 16 in trySelect()
1154 : (SplatBitSize == 32 ? Mips::FILL_W in trySelect()
1167 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) { in trySelect()
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| H A D | MipsISelDAGToDAG.cpp | 237 unsigned SplatBitSize; in selectVecAddAsVecSubIfProfitable() local
240 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, in selectVecAddAsVecSubIfProfitable()
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| H A D | MipsSEISelLowering.cpp | 534 unsigned SplatBitSize; in isVSplat() local
559 unsigned SplatBitSize; in isVectorAllOnes() local
843 unsigned SplatBitSize; in performDSPShiftCombine() local
852 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, in performDSPShiftCombine()
854 (SplatBitSize != EltSize) || in performDSPShiftCombine()
2457 unsigned SplatBitSize; in lowerBUILD_VECTOR() local
2463 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, in lowerBUILD_VECTOR()
2465 !Subtarget.isLittle()) && SplatBitSize <= 64) { in lowerBUILD_VECTOR()
2467 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && in lowerBUILD_VECTOR()
2468 SplatBitSize != 64) in lowerBUILD_VECTOR()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6511 unsigned SplatBitSize; in getVShiftImm() local
6906 SplatBitSize = 32; in isVMOVModifiedImm()
6908 switch (SplatBitSize) { in isVMOVModifiedImm()
7804 unsigned SplatBitSize; in LowerBUILD_VECTOR() local
7813 (SplatBitSize == 8 || SplatBitSize == 16 || SplatBitSize == 32) && in LowerBUILD_VECTOR()
7859 (SplatBitSize == 8 || SplatBitSize == 16 || SplatBitSize == 32)) { in LowerBUILD_VECTOR()
14184 unsigned SplatBitSize; in PerformANDCombine() local
14188 if (SplatBitSize == 8 || SplatBitSize == 16 || SplatBitSize == 32 || in PerformANDCombine()
14480 unsigned SplatBitSize; in PerformORCombine() local
14484 if (SplatBitSize == 8 || SplatBitSize == 16 || SplatBitSize == 32 || in PerformORCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 746 if (SplatBitSize > 64) in isVectorConstantLegal()
751 int64_t SignedValue = SignExtend64(Value, SplatBitSize); in isVectorConstantLegal()
755 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize), in isVectorConstantLegal()
756 SystemZ::VectorBits / SplatBitSize); in isVectorConstantLegal()
761 if (TII->isRxSBGMask(Value, SplatBitSize, Start, End)) { in isVectorConstantLegal()
765 OpVals.push_back(Start - (64 - SplatBitSize)); in isVectorConstantLegal()
766 OpVals.push_back(End - (64 - SplatBitSize)); in isVectorConstantLegal()
768 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize), in isVectorConstantLegal()
819 SplatBitSize = Width; in SystemZVectorConstantInfo()
5612 unsigned SplatBitSize; in lowerShift() local
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| H A D | SystemZISelLowering.h | 775 unsigned SplatBitSize = 0; member
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 9177 unsigned SplatBitSize; in LowerBUILD_VECTOR() local
9187 if (BVNIsConstantSplat && (SplatBitSize == 64) && in LowerBUILD_VECTOR()
9226 if (!BVNIsConstantSplat || SplatBitSize > 32) { in LowerBUILD_VECTOR()
9314 unsigned SplatSize = SplatBitSize / 8; in LowerBUILD_VECTOR()
9347 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> in LowerBUILD_VECTOR()
9348 (32-SplatBitSize)); in LowerBUILD_VECTOR()
9406 unsigned TypeShiftAmt = i & (SplatBitSize-1); in LowerBUILD_VECTOR()
9787 unsigned SplatBitSize; in lowerToXXSPLTI32DX() local
9791 SplatBitSize > 32) in lowerToXXSPLTI32DX()
9817 for (; SplatBitSize < 32; SplatBitSize <<= 1) in lowerToXXSPLTI32DX()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2525 unsigned SplatBitSize; in performVectorTruncZeroCombine() local
2528 Splat->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, in performVectorTruncZeroCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10704 unsigned SplatBitSize; in resolveBuildVector() local
10706 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { in resolveBuildVector()
10707 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize; in resolveBuildVector()
10710 CnstBits <<= SplatBitSize; in resolveBuildVector()
10711 UndefBits <<= SplatBitSize; in resolveBuildVector()
11875 unsigned SplatBitSize; in getVShiftImm() local
11877 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, in getVShiftImm()
11879 SplatBitSize > ElementBits) in getVShiftImm()
16097 unsigned SplatBitSize; in tryCombineShiftImm() local
16099 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, in tryCombineShiftImm()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 1983 unsigned &SplatBitSize, bool &HasAnyUndefs,
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 158 unsigned SplatBitSize; in isConstantSplatVector() local
161 return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs, in isConstantSplatVector()
163 EltSize == SplatBitSize; in isConstantSplatVector()
11395 unsigned &SplatBitSize, in isConstantSplat() argument
11456 SplatBitSize = VecWidth; in isConstantSplat()
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| H A D | DAGCombiner.cpp | 6274 unsigned SplatBitSize; in visitAND() local
6277 SplatBitSize, HasAnyUndefs); in visitAND()
6292 if (EltBitWidth > SplatBitSize) in visitAND()
6294 SplatBitSize < EltBitWidth; SplatBitSize = SplatBitSize * 2) in visitAND()
6295 SplatValue |= SplatValue.shl(SplatBitSize); in visitAND()
6299 if ((SplatBitSize % EltBitWidth) == 0) { in visitAND()
6301 for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i) in visitAND()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6682 unsigned SplatBitSize; in getAVX512Node() local
9499 unsigned NumElm = SplatBitSize / ScalarSize; in getConstantVector()
9618 unsigned SplatBitSize; in lowerBuildVectorAsBroadcast() local
9622 SplatBitSize > VT.getScalarSizeInBits() && in lowerBuildVectorAsBroadcast()
9623 SplatBitSize < VT.getSizeInBits()) { in lowerBuildVectorAsBroadcast()
9633 if (SplatBitSize == 32 || SplatBitSize == 64 || in lowerBuildVectorAsBroadcast()
9634 (SplatBitSize < 32 && Subtarget.hasAVX2())) { in lowerBuildVectorAsBroadcast()
9637 MVT CVT = MVT::getIntegerVT(SplatBitSize); in lowerBuildVectorAsBroadcast()
9638 Type *ScalarTy = Type::getIntNTy(*Ctx, SplatBitSize); in lowerBuildVectorAsBroadcast()
9641 unsigned Repeat = VT.getSizeInBits() / SplatBitSize; in lowerBuildVectorAsBroadcast()
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