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Searched refs:SimpleTy (Results 1 – 25 of 63) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DMachineValueType.h393 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
394 SimpleTy == MVT::v16i1 || SimpleTy == MVT::v1f16); in is16BitVector()
399 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
400 SimpleTy == MVT::v2i16 || SimpleTy == MVT::v1i32 || in is32BitVector()
401 SimpleTy == MVT::v2f16 || SimpleTy == MVT::v2bf16 || in is32BitVector()
407 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 || in is64BitVector()
420 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); in is128BitVector()
426 SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
428 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64 || in is256BitVector()
461 return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny || in isOverloaded()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h48 if (V.SimpleTy != VT.V.SimpleTy)
50 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
66 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getIntegerVT()
76 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
85 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE) in getVectorVT()
130 return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE; in isSimple()
471 return V.SimpleTy; in getRawBits()
480 if (L.V.SimpleTy == R.V.SimpleTy) in operator()
483 return L.V.SimpleTy < R.V.SimpleTy; in operator()
H A DTargetLowering.h924 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
955 return ValueTypeActions[VT.SimpleTy]; in getTypeAction()
959 ValueTypeActions[VT.SimpleTy] = Action; in setTypeAction()
1515 return RegisterTypeForVT[VT.SimpleTy]; in getRegisterType()
2289 RegClassForVT[VT.SimpleTy] = RC; in addRegisterClass()
2327 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift); in setLoadExtAction()
2328 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift; in setLoadExtAction()
2345 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action; in setTruncStoreAction()
2429 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
3301 unsigned Ty = (unsigned)VT.SimpleTy; in setIndexedModeAction()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp133 if (LocVT.SimpleTy == MVT::i64 || (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32)) in CC_AArch64_Custom_Block()
135 else if (LocVT.SimpleTy == MVT::f16) in CC_AArch64_Custom_Block()
137 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) in CC_AArch64_Custom_Block()
139 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
141 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
162 unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1; in CC_AArch64_Custom_Block()
H A DAArch64FastISel.cpp319 switch (VT.SimpleTy) { in getImplicitScaleFactor()
1142 switch (RetVT.SimpleTy) { in emitAddSub()
1161 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1455 switch (VT.SimpleTy) { in emitCmp()
1810 switch (VT.SimpleTy) { in emitLoad()
2040 switch (VT.SimpleTy) { in emitStoreRelease()
2099 switch (VT.SimpleTy) { in emitStore()
2658 switch (VT.SimpleTy) { in selectSelect()
4025 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
4128 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
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/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1072 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1099 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1316 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1327 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLDGLDU()
1769 Value.getNode()->getSimpleValueType(0).SimpleTy; in tryStore()
2121 Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, in tryLoadParam()
3712 switch (SrcTy.SimpleTy) { in GetConvertOpcode()
3716 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3727 switch (DestTy.SimpleTy) { in GetConvertOpcode()
3738 switch (DestTy.SimpleTy) { in GetConvertOpcode()
[all …]
H A DNVPTXTargetTransformInfo.cpp448 if (LT.second.SimpleTy == MVT::i64) in getArithmeticInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp241 auto isHvxTy = [this, IncludeBool](MVT SimpleTy) { in isTypeForHVX() argument
242 if (isHVXVectorType(SimpleTy, IncludeBool)) in isTypeForHVX()
244 auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy); in isTypeForHVX()
253 MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen); in isTypeForHVX() local
254 if (SimpleTy.isValid() && isHvxTy(SimpleTy)) in isTypeForHVX()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.h88 return (Words[T.SimpleTy / WordWidth] >> (T.SimpleTy % WordWidth)) & 1; in count()
91 bool V = count(T.SimpleTy); in insert()
92 Words[T.SimpleTy / WordWidth] |= WordType(1) << (T.SimpleTy % WordWidth); in insert()
102 Words[T.SimpleTy / WordWidth] &= ~(WordType(1) << (T.SimpleTy % WordWidth)); in erase()
712 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType()
H A DInfoByHwMode.cpp76 StringRef N = llvm::getEnumName(T.SimpleTy); in getMVTName()
H A DDAGISelMatcherGen.cpp38 VT = VVT.getSimple().SimpleTy; in getRegisterValueType()
45 assert((!T.isSimple() || T.getSimple().SimpleTy == VT) && in getRegisterValueType()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp336 switch (VT.SimpleTy) { in X86FastEmitLoad()
1928 switch (VT.SimpleTy) { in X86SelectDivRem()
2674 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
2814 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3003 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3116 switch (VT.SimpleTy) { in fastLowerArguments()
3676 switch (VT.SimpleTy) { in X86MaterializeInt()
3696 switch (VT.SimpleTy) { in X86MaterializeInt()
3732 switch (VT.SimpleTy) { in X86MaterializeFP()
3841 switch (VT.SimpleTy) { in fastMaterializeConstant()
[all …]
H A DX86ISelDAGToDAG.cpp4502 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4508 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
4513 switch (TestVT.SimpleTy) { in getVPTESTMOpc()
5056 switch (NVT.SimpleTy) { in Select()
5133 switch (NVT.SimpleTy) { in Select()
5215 switch (NVT.SimpleTy) { in Select()
5333 switch (NVT.SimpleTy) { in Select()
5341 switch (NVT.SimpleTy) { in Select()
5352 switch (NVT.SimpleTy) { in Select()
5414 switch (NVT.SimpleTy) { in Select()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp87 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
H A DAMDGPUTargetTransformInfo.cpp529 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getArithmeticInstrCost()
698 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp138 switch (VT.SimpleTy) { in selectIndexedLoad()
182 switch (VT.SimpleTy) { in selectIndexedProgMemLoad()
394 switch (VT.SimpleTy) { in select()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp304 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
330 switch (VT.SimpleTy) { in tryIndexedLoad()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp324 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; in LowerFormalArguments() local
325 switch (SimpleTy) { in LowerFormalArguments()
334 SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp126 switch (Type.SimpleTy) { in toValType()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp504 switch (VT.SimpleTy) { in getOUTLINE_ATOMIC()
581 switch (VT.SimpleTy) { \ in getSYNC()
752 OpActions[(unsigned)VT.SimpleTy][NT] = Expand; in initActions()
953 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); in getTypeConversion()
954 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1252 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1517 return getPointerTy(DL).SimpleTy; in getSetCCResultType()
H A DValueTypes.cpp153 switch (V.SimpleTy) { in getEVTString()
184 switch (V.SimpleTy) { in getTypeForEVT()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp802 switch (VT.SimpleTy) { in ARMSimplifyAddress()
858 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
905 switch (VT.SimpleTy) { in ARMEmitLoad()
1044 switch (VT.SimpleTy) { in ARMEmitStore()
1381 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1815 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
1908 switch (ArgVT.SimpleTy) { in ProcessCallArgs()
3045 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
H A DARMCallingConv.cpp198 switch (LocVT.SimpleTy) { in CC_ARM_AAPCS_Custom_Aggregate()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp757 switch (VT.SimpleTy) { in emitLoad()
811 switch (VT.SimpleTy) { in emitStore()
1365 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
1826 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1844 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1870 switch (SrcVT.SimpleTy) { in emitIntZExt()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp524 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
527 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()

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