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Searched refs:ShiftVal (Results 1 – 25 of 26) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
268 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
288 ShiftVal = 12; in getAddSubImmOpValue()
290 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getAddSubImmOpValue()
546 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local
547 assert((ShiftVal == 0 || ShiftVal == 8) && in getImm8OptLsl()
552 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getImm8OptLsl()
573 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
574 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
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H A DAArch64InstPrinter.cpp1081 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1093 if (ShiftVal != 0) in printArithExtend()
1094 O << ", lsl #" << ShiftVal; in printArithExtend()
1099 if (ShiftVal != 0) in printArithExtend()
1100 O << " #" << ShiftVal; in printArithExtend()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp390 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
391 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); in getIntMatCost()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h307 bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
308 void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
322 unsigned &ShiftVal);
323 void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1535 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchShiftOfShiftedLogic()
1607 ShiftVal = MaybeImmVal->Value.exactLogBase2(); in matchCombineMulToShl()
1608 return (static_cast<int32_t>(ShiftVal) != -1); in matchCombineMulToShl()
1616 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
1917 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchCombineShiftToUnmerge()
1918 return ShiftVal >= Size / 2 && ShiftVal < Size; in matchCombineShiftToUnmerge()
1928 assert(ShiftVal >= HalfSize); in applyCombineShiftToUnmerge()
1934 unsigned NarrowShiftAmt = ShiftVal - HalfSize; in applyCombineShiftToUnmerge()
1970 if (ShiftVal == HalfSize) { in applyCombineShiftToUnmerge()
1974 } else if (ShiftVal == Size - 1) { in applyCombineShiftToUnmerge()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1234 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1239 ShiftVal, SetFlags, WantResult); in emitAddSub()
1256 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1262 ShiftVal, SetFlags, WantResult); in emitAddSub()
1618 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
4589 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4617 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4652 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
4683 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
4686 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt); in selectShift()
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H A DAArch64ISelDAGToDAG.cpp562 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
563 if (ShiftVal > 3) in isWorthFoldingSHL()
848 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
855 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
856 if (ShiftVal > 4) in SelectArithExtendedRegister()
892 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
901 unsigned ShiftVal = 0; in SelectArithUXTXRegister() local
910 ShiftVal = CSD->getZExtValue(); in SelectArithUXTXRegister()
911 if (ShiftVal > 4) in SelectArithUXTXRegister()
1130 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
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H A DAArch64InstrInfo.cpp885 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
886 if (ShiftVal == 0) in isFalkorShiftExtFast()
888 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
912 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
913 return ShiftVal == 0 || in isFalkorShiftExtFast()
914 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
920 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
921 return ShiftVal == 0 || in isFalkorShiftExtFast()
922 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
H A DAArch64TargetTransformInfo.cpp163 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
164 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp789 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
790 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal); in CreateWideLoad()
/llvm-project-15.0.7/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp547 unsigned ShiftVal = AArch64_AM::getArithShiftValue(OperandExtension); in analyzeIndirectBranchFragment() local
550 if (ShiftVal != 2) in analyzeIndirectBranchFragment()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2508 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
2517 ShiftVal = Amount; in isSimpleShift()
2666 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2669 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2670 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
2671 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
2677 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2680 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2681 (MaskVal << ShiftVal != 0) && in adjustForTestUnderMask()
2682 ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal && in adjustForTestUnderMask()
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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2390 auto ShiftVal = DAG.getSplatValue(Op.getOperand(1)); in LowerShift() local
2391 if (!ShiftVal) in LowerShift()
2395 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32); in LowerShift()
2412 return DAG.getNode(Opcode, DL, Op.getValueType(), Op.getOperand(0), ShiftVal); in LowerShift()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2161 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2166 ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, in SelectS_BFE()
2182 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2183 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
2187 ReplaceNode(N, getBFE32(false, SDLoc(N), And.getOperand(0), ShiftVal, in SelectS_BFE()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp388 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
389 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
395 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
H A DX86TargetTransformInfo.cpp4872 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
4873 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
H A DX86ISelLowering.cpp8526 if ((ShiftVal % 8) != 0) in getFauxShuffleMask()
19822 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
19833 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
37128 if (ShiftVal.uge(VTBits)) in ComputeNumSignBitsForTargetNode()
37131 if (ShiftVal.uge(Tmp)) in ComputeNumSignBitsForTargetNode()
37139 if (ShiftVal.uge(VTBits - 1)) in ComputeNumSignBitsForTargetNode()
37142 ShiftVal += Tmp; in ComputeNumSignBitsForTargetNode()
37143 return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue(); in ComputeNumSignBitsForTargetNode()
47113 ShiftVal = NumBitsPerElt - 1; in combineVectorShiftImm()
47117 if (!ShiftVal) in combineVectorShiftImm()
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/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp508 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
511 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
518 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
H A DInstCombineCompares.cpp2123 const APInt *ShiftVal; in foldICmpShlConstant() local
2124 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
2125 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
/llvm-project-15.0.7/llvm/lib/IR/
H A DAutoUpgrade.cpp1228 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in UpgradeX86ALIGNIntrinsics() local
1237 ShiftVal &= (NumElts - 1); in UpgradeX86ALIGNIntrinsics()
1241 if (ShiftVal >= 32) in UpgradeX86ALIGNIntrinsics()
1246 if (ShiftVal > 16) { in UpgradeX86ALIGNIntrinsics()
1247 ShiftVal -= 16; in UpgradeX86ALIGNIntrinsics()
1256 unsigned Idx = ShiftVal + i; in UpgradeX86ALIGNIntrinsics()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5064 unsigned ShiftVal = 0; in Select() local
5069 ShiftVal = 1; in Select()
5073 ShiftVal = 1; in Select()
5078 ShiftVal = 3; in Select()
5082 ShiftVal = 3; in Select()
5087 ShiftVal = 2; in Select()
5091 ShiftVal = 2; in Select()
5123 SDValue Ops[] = {Move, getI32Imm((32 - (4 + ShiftVal)) & 31, dl), in Select()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1984 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
2000 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp6551 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local
6554 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}}; in selectShiftedRegister()
6642 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
6659 ShiftVal = *MaybeShiftVal; in selectArithExtendedRegister()
6660 if (ShiftVal > 4) in selectArithExtendedRegister()
6696 MIB.addImm(getArithExtendImm(Ext, ShiftVal)); in selectArithExtendedRegister()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp13753 if (ShiftVal >= 32) in EmitX86BuiltinExpr()
13758 if (ShiftVal > 16) { in EmitX86BuiltinExpr()
13759 ShiftVal -= 16; in EmitX86BuiltinExpr()
13768 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
13790 ShiftVal &= NumElts - 1; in EmitX86BuiltinExpr()
13794 Indices[i] = i + ShiftVal; in EmitX86BuiltinExpr()
13879 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
13909 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
13937 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
13959 if (ShiftVal >= NumElts) in EmitX86BuiltinExpr()
[all …]
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DValueTracking.cpp2604 auto ShiftVal = Shift->getLimitedValue(BitWidth - 1); in isKnownNonZero() local
2606 if (Known.countMaxLeadingZeros() < BitWidth - ShiftVal) in isKnownNonZero()
2609 if (Known.countMinTrailingZeros() >= ShiftVal) in isKnownNonZero()

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