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Searched refs:Sched (Results 1 – 25 of 87) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepTimingClasses.h21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp95 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
96 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
98 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
103 case PPC::Sched::IIC_LdStLWA: in mustComeFirst()
104 case PPC::Sched::IIC_LdStSTU: in mustComeFirst()
109 case PPC::Sched::IIC_LdStLDUX: in mustComeFirst()
113 case PPC::Sched::IIC_LdStSTUX: in mustComeFirst()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrExtension.td50 OpSize32, Sched<[WriteALU]>;
58 OpSize32, Sched<[WriteALU]>;
76 OpSize32, Sched<[WriteALU]>;
142 Sched<[WriteALU]>;
146 TB, Sched<[WriteALULd]>;
150 Sched<[WriteALU]>;
154 TB, Sched<[WriteALULd]>;
188 TB, Sched<[WriteALU]>;
192 TB, Sched<[WriteALULd]>;
195 TB, Sched<[WriteALU]>;
[all …]
H A DX86InstrControl.td129 OpSize16, Sched<[WriteJump]>;
136 OpSize32, Sched<[WriteJump]>;
143 Sched<[WriteJump]>;
146 Sched<[WriteJumpLd]>;
180 Sched<[WriteJump]>, NOTRACK;
232 Sched<[WriteJump]>;
239 Sched<[WriteJumpLd]>;
243 Sched<[WriteJump]>;
249 Sched<[WriteJumpLd]>;
301 []>, Sched<[WriteJump]>;
[all …]
H A DX86InstrMMX.td41 Sched<[sched]> {
59 Sched<[sched]>;
69 Sched<[schedImm]>;
79 Sched<[sched]>;
84 Sched<[sched.Folded]>;
97 Sched<[sched]>;
114 Sched<[sched]>;
128 Sched<[sched]>;
131 Sched<[sched.Folded]>;
140 Sched<[WriteCvtI2PS]>;
[all …]
H A DX86InstrXOP.td51 Sched<[sched.Folded, sched.ReadAfterFold]>;
62 Sched<[sched.Folded, sched.ReadAfterFold]>;
73 Sched<[sched.Folded, sched.ReadAfterFold]>;
101 XOP, Sched<[sched]>;
147 XOP, Sched<[sched]>;
177 Sched<[sched]>;
255 XOP_4V, Sched<[sched]>;
291 XOP_4V, Sched<[sched]>;
337 Sched<[sched]>;
426 Sched<[sched]>;
[all …]
H A DX86InstrSSE.td31 Sched<[sched]>;
54 Sched<[sched]>;
77 Sched<[sched]>;
5782 Sched<[Sched]>;
5788 Sched<[Sched.Folded]>;
7040 Sched<[Sched]>, VEX;
7048 Sched<[Sched]>, VEX;
7765 Sched<[Sched]>, VEX_4V, VEX_L;
7773 Sched<[Sched.Folded, Sched.ReadAfterFold]>, VEX_4V, VEX_L;
7791 Sched<[Sched]>, VEX, VEX_L;
[all …]
H A DX86InstrFMA.td44 Sched<[sched]>;
64 []>, Sched<[sched]>;
84 []>, Sched<[sched]>;
186 Sched<[sched]>;
206 []>, Sched<[sched]>;
226 []>, Sched<[sched]>;
276 []>, Sched<[sched]>;
400 Sched<[sched]>;
437 []>, VEX_W, VEX_LIG, Sched<[sched]>;
477 VEX_W, Sched<[sched.XMM]>;
[all …]
H A DX86InstrArithmetic.td48 class SchedLoadReg<X86FoldableSchedWrite Sched> : Sched<[Sched.Folded,
52 Sched.ReadAfterFold, Sched.ReadAfterFold]>;
82 Sched<[WriteIMul64]>;
112 Sched<[WriteIMul8]>;
124 Sched<[WriteIMul64]>;
646 Sched<[sched]>;
680 Sched<[sched]> {
696 Sched<[WriteALU]> {
752 Sched<[sched]> {
783 Sched<[sched]> {
[all …]
H A DX86InstrAVX512.td3420 _.ExeDomain>, EVEX, Sched<[Sched.RR]>,
3429 EVEX, EVEX_KZ, Sched<[Sched.RR]>;
3437 _.ExeDomain>, EVEX, Sched<[Sched.RM]>,
3448 EVEX, EVEX_K, Sched<[Sched.RR]>;
3457 EVEX, EVEX_K, Sched<[Sched.RM]>;
3465 _.ExeDomain>, EVEX, EVEX_KZ, Sched<[Sched.RM]>;
3534 Sched<[Sched.RR]>;
3541 Sched<[Sched.RR]>;
3549 _.ExeDomain>, EVEX, Sched<[Sched.MR]>,
9189 EVEX_B, AVX512AIi8Base, Sched<[Sched]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td119 class VLSEGSched<int nf, int eew> : Sched<[
121 class VSSEGSched<int nf, int eew> : Sched<[
124 class VLSEGFFSched<int nf, int eew> : Sched<[
127 class VLSSEGSched<int nf, int eew> : Sched<[
130 class VSSSEGSched<int nf, int eew> : Sched<[
134 class VLUXSEGSched<int nf, int eew> : Sched<[
137 class VLOXSEGSched<int nf, int eew> : Sched<[
140 class VSUXSEGSched<int nf, int eew> : Sched<[
143 class VSOXSEGSched<int nf, int eew> : Sched<[
825 Sched<[schedrw, ReadVLDX]>;
[all …]
H A DRISCVInstrInfoM.td29 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
31 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
33 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
35 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
40 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
42 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
44 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
46 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
51 Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
56 Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
[all …]
H A DRISCVInstrInfoC.td307 Sched<[WriteLDW, ReadMemBase]> {
326 Sched<[WriteLDD, ReadMemBase]> {
368 Sched<[WriteNop]>
377 Sched<[WriteIALU, ReadIALU]> {
411 Sched<[WriteIALU]> {
433 Sched<[WriteIALU]> {
445 Sched<[WriteIALU, ReadIALU]> {
530 Sched<[WriteIALU, ReadIALU]>;
580 Sched<[]> {
622 Sched<[WriteIALU]> {
[all …]
H A DRISCVInstrInfoZb.td485 Sched<[WriteCLZ, ReadCLZ]>;
487 Sched<[WriteCTZ, ReadCTZ]>;
489 Sched<[WriteCPOP, ReadCPOP]>;
503 Sched<[WriteIALU, ReadIALU]>;
505 Sched<[WriteIALU, ReadIALU]>;
510 Sched<[WriteCRCB, ReadCRCB]>;
512 Sched<[WriteCRCH, ReadCRCH]>;
639 Sched<[WriteORCB, ReadORCB]>;
644 Sched<[]>;
648 Sched<[]>;
[all …]
H A DRISCVInstrInfoZicbo.td58 def CBO_CLEAN : CBO_r<0b000000000001, "cbo.clean">, Sched<[]>;
59 def CBO_FLUSH : CBO_r<0b000000000010, "cbo.flush">, Sched<[]>;
60 def CBO_INVAL : CBO_r<0b000000000000, "cbo.inval">, Sched<[]>;
64 def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>;
68 def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>;
69 def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>;
70 def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>;
H A DRISCVInstrInfoA.td61 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
63 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
65 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
67 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
69 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
71 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
73 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
75 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
77 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
85 Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
[all …]
H A DRISCVInstrInfo.td489 Sched<[WriteJmp, ReadJmp, ReadJmp]> {
527 Sched<[WriteIALU, ReadIALU]>;
534 Sched<[WriteShiftImm, ReadShiftImm]>;
562 Sched<[WriteShiftImm32, ReadShiftImm32]>;
604 Sched<[WriteJalr, ReadJalr]>;
695 Sched<[]> {
705 Sched<[]> {
731 Sched<[WriteIALU32, ReadIALU32]>;
754 def URET : Priv<"uret", 0b0000000>, Sched<[]> {
760 def SRET : Priv<"sret", 0b0001000>, Sched<[]> {
[all …]
H A DRISCVInstrInfoVPseudos.td2106 Sched<[WriteVIMovI]>;
2112 Sched<[WriteVIMovI]>;
2123 Sched<[WriteVFMovV, ReadVFMovF]>;
2126 Sched<[WriteVFMovV, ReadVFMovF]>;
2183 Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
2200 Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
2515 Sched<[WriteVICALUI, ReadVIALUCV]>;
4400 Sched<[WriteVLDM, ReadVLDX]>;
4402 Sched<[WriteVSTM, ReadVSTX]>;
4964 Sched<[WriteVIMovVX, ReadVIMovVX]>,
[all …]
H A DRISCVInstrInfoZfh.td127 Sched<[WriteFSqrt16, ReadFSqrt16]>;
143 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>;
151 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>;
159 Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
163 Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
168 Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]>;
172 Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>;
183 Sched<[WriteFClass16, ReadFClass16]>;
194 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>;
202 Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb.td1012 Sched<[WriteALU]>;
1100 Sched<[WriteALU]>;
1299 Sched<[WriteALU]>;
1315 Sched<[WriteALU]>;
1349 Sched<[WriteALU]>;
1366 Sched<[WriteALU]>;
1373 Sched<[WriteALU]>;
1380 Sched<[WriteALU]>;
1387 Sched<[WriteALU]>;
1393 Sched<[WriteALU]>;
[all …]
H A DARMInstrNEON.td945 Sched<[WriteVLD4]> {
1258 []>, Sched<[WriteVLD2]> {
1294 Sched<[WriteVLD2]> {
1377 Sched<[WriteVLD2]> {
1549 Sched<[WriteVLD2]> {
1846 []>, Sched<[WriteVST4]> {
2069 "", []>, Sched<[WriteVST4]> {
2156 Sched<[WriteVST1]> {
2208 Sched<[WriteVST1]> {
2243 "", []>, Sched<[WriteVST1]> {
[all …]
H A DARMInstrVFP.td408 Sched<[WriteFPALU64]>;
451 Sched<[WriteFPALU32]>;
709 Sched<[WriteFPCVT]> {
755 Sched<[WriteFPCVT]>;
767 Sched<[WriteFPCVT]>;
789 Sched<[WriteFPCVT]>;
803 Sched<[WriteFPCVT]>;
1825 Sched<[WriteFPCVT]>;
1831 Sched<[WriteFPCVT]>;
1998 Sched<[]> {
[all …]
H A DARMInstrThumb2.td1629 Sched<[WriteLd]>;
1632 Sched<[WriteLd]>;
1635 Sched<[WriteLd]>;
1674 Sched<[WriteST]>;
1686 Sched<[WriteST]>;
1697 Sched<[WriteST]>;
1708 Sched<[WriteST]>;
1807 Sched<[WriteST]> {
3888 Sched<[WriteBr]>;
3893 Sched<[WriteBr]>;
[all …]
H A DARMInstrInfo.td2671 Sched<[WriteBr]> {
4722 Sched<[WriteDIV]>;
4728 Sched<[WriteDIV]>;
4737 Sched<[WriteALU]>;
4743 Sched<[WriteALU]>;
4748 Sched<[WriteALU]>;
4755 Sched<[WriteALU]>;
4769 Sched<[WriteALU]>;
4994 Sched<[WriteBr]>;
4999 Sched<[WriteBr]>;
[all …]
/llvm-project-15.0.7/polly/lib/Transform/
H A DManualOptimizer.cpp210 const isl::schedule &Sched) { in applyOneTransformation() argument
212 Transformer.visit(Sched); in applyOneTransformation()
287 polly::applyManualTransformations(Scop *S, isl::schedule Sched, in applyManualTransformations() argument
293 SearchTransformVisitor::applyOneTransformation(S, &D, ORE, Sched); in applyManualTransformations()
300 Sched = Result; in applyManualTransformations()
303 return Sched; in applyManualTransformations()

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