Lines Matching refs:Sched

48 class SchedLoadReg<X86FoldableSchedWrite Sched> : Sched<[Sched.Folded,
52   Sched.ReadAfterFold, Sched.ReadAfterFold]>;
65                 (implicit EFLAGS)]>, Sched<[WriteIMul8]>;
70                []>, OpSize16, Sched<[WriteIMul16]>;
76                OpSize32, Sched<[WriteIMul32]>;
82                 Sched<[WriteIMul64]>;
112                 Sched<[WriteIMul8]>;
116                 OpSize16, Sched<[WriteIMul16]>;
120                 OpSize32, Sched<[WriteIMul32]>;
124                  Sched<[WriteIMul64]>;
158                  Sched<[WriteIMul16Reg]>, TB, OpSize16;
163                  Sched<[WriteIMul32Reg]>, TB, OpSize32;
169                   Sched<[WriteIMul64Reg]>, TB;
178                  Sched<[WriteIMul16Reg.Folded, WriteIMul16Reg.ReadAfterFold]>, TB, OpSize16;
184                  Sched<[WriteIMul32Reg.Folded, WriteIMul32Reg.ReadAfterFold]>, TB, OpSize32;
190                   Sched<[WriteIMul64Reg.Folded, WriteIMul32Reg.ReadAfterFold]>, TB;
206                      Sched<[WriteIMul16Imm]>, OpSize16;
212                       Sched<[WriteIMul16Imm]>, OpSize16;
218                       Sched<[WriteIMul32Imm]>, OpSize32;
224                      Sched<[WriteIMul32Imm]>, OpSize32;
230                       Sched<[WriteIMul64Imm]>;
236                          Sched<[WriteIMul64Imm]>;
245                      Sched<[WriteIMul16Imm.Folded]>, OpSize16;
251                       Sched<[WriteIMul16Imm.Folded]>, OpSize16;
258                      Sched<[WriteIMul32Imm.Folded]>, OpSize32;
264                       Sched<[WriteIMul32Imm.Folded]>, OpSize32;
271                       Sched<[WriteIMul64Imm.Folded]>;
278                          Sched<[WriteIMul64Imm.Folded]>;
285                "div{b}\t$src", []>, Sched<[WriteDiv8]>;
288                "div{w}\t$src", []>, Sched<[WriteDiv16]>, OpSize16;
291                "div{l}\t$src", []>, Sched<[WriteDiv32]>, OpSize32;
295                 "div{q}\t$src", []>, Sched<[WriteDiv64]>;
317                "idiv{b}\t$src", []>, Sched<[WriteIDiv8]>;
320                "idiv{w}\t$src", []>, Sched<[WriteIDiv16]>, OpSize16;
323                "idiv{l}\t$src", []>, Sched<[WriteIDiv32]>, OpSize32;
327                 "idiv{q}\t$src", []>, Sched<[WriteIDiv64]>;
646     Sched<[sched]>;
680     Sched<[sched]> {
696     Sched<[WriteALU]> {
709     Sched<[sched.Folded, sched.ReadAfterFold]>;
718     Sched<[sched.Folded, sched.ReadAfterFold,
752     Sched<[sched]> {
783     Sched<[sched]> {
821            (implicit EFLAGS)]>, Sched<[WriteALURMW,
833              (implicit EFLAGS)]>, Sched<[WriteADCRMW,
846             Sched<[WriteALU.Folded, ReadDefault, ReadDefault, ReadDefault,
864              (implicit EFLAGS)]>, Sched<[WriteALURMW]>;
871              (implicit EFLAGS)]>, Sched<[WriteADCRMW]>;
879             Sched<[WriteALU.Folded]>;
896               (implicit EFLAGS)]>, Sched<[WriteALURMW]>;
904               (implicit EFLAGS)]>, Sched<[WriteADCRMW]>;
912              Sched<[WriteALU.Folded]>;
919         mnemonic, operands, []>, Sched<[sched]> {
1214                      Sched<[WriteALU]>;
1467             Sched<[sched]>;
1472            Sched<[sched.Folded, sched.ReadAfterFold]>;
1500              []>, T8XD, VEX_4V, Sched<[WriteIMulH, sched]>;
1506              Sched<[WriteIMulHLd, sched.Folded,
1515                     []>, Sched<[sched]>;
1519                     []>, Sched<[sched.Folded]>;