Lines Matching refs:Sched
392 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
405 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
425 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
436 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
457 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
469 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
485 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
494 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
504 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
508 [(ARMseretflag)]>, Sched<[WriteBr]>;
513 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
526 Requires<[IsThumb]>, Sched<[WriteBrL]> {
539 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
553 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
561 Sched<[WriteBrL]>;
568 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> {
577 Requires<[IsThumb, Has8MSecExt]>, Sched<[WriteBr]>;
583 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
590 Requires<[IsThumb]>, Sched<[WriteBr]>;
602 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
615 Sched<[WriteBrTbl]>;
621 Sched<[WriteBrTbl]> {
634 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
650 Requires<[IsThumb]>, Sched<[WriteBr]>;
660 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
670 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
680 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
695 T1Encoding<{0,1,0,0,1,?}>, Sched<[WriteLd]> {
709 T1LdStSP<{1,?,?}>, Sched<[WriteLd]> {
760 load>, Sched<[WriteLd]>;
766 zextloadi8>, Sched<[WriteLd]>;
772 zextloadi16>, Sched<[WriteLd]>;
779 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>;
786 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr_sext:$addr))]>, Sched<[WriteLd]>;
792 T1LdStSP<{0,?,?}>, Sched<[WriteST]> {
803 store>, Sched<[WriteST]>;
809 truncstorei8>, Sched<[WriteST]>;
815 truncstorei16>, Sched<[WriteST]>;
875 T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> {
885 T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> {
972 []>, Sched<[WriteALU]>;
980 Sched<[WriteALU]> {
990 Sched<[WriteALU]>;
998 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1012 Sched<[WriteALU]>;
1019 Sched<[WriteALU]>;
1026 Sched<[WriteALU]>;
1034 Sched<[WriteALU]>;
1040 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
1074 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1082 Sched<[WriteALU]> {
1092 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1100 Sched<[WriteALU]>;
1116 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1125 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
1138 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
1142 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
1159 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1167 Sched<[WriteALU]> {
1177 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1185 Sched<[WriteALU]> {
1195 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1202 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1220 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1230 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1246 T1DataProcessing<0b1101>, Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
1261 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1269 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1277 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1284 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1291 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1299 Sched<[WriteALU]>;
1306 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1315 Sched<[WriteALU]>;
1323 Sched<[WriteALU]> {
1333 Sched<[WriteALU]>;
1349 Sched<[WriteALU]>;
1366 Sched<[WriteALU]>;
1373 Sched<[WriteALU]>;
1380 Sched<[WriteALU]>;
1387 Sched<[WriteALU]>;
1393 Sched<[WriteALU]>;
1399 Sched<[WriteALU]>;
1415 Sched<[WriteALU]>;
1424 Sched<[WriteALU]>;
1432 Sched<[WriteALU]>;
1460 Sched<[WriteALU]>;
1468 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1483 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1493 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1498 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1506 IIC_Br, []>, Sched<[WriteBr]>;
1510 IIC_Br, []>, Sched<[WriteBr]>;
1524 Sched<[WriteBr]>;
1743 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1749 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1787 NoItinerary, []>, Sched<[]>;
1791 NoItinerary, []>, Sched<[]>;
1795 NoItinerary, []>, Sched<[]>;