Lines Matching refs:Sched
1532 Sched<[WriteALU, ReadALU]> {
1545 Sched<[WriteALU, ReadALU, ReadALU]> {
1561 Sched<[WriteALUsi, ReadALU]> {
1577 Sched<[WriteALUsr, ReadALUsr]> {
1605 Sched<[WriteALU, ReadALU]> {
1618 Sched<[WriteALU, ReadALU, ReadALU]> {
1633 Sched<[WriteALUsi, ReadALU]> {
1649 Sched<[WriteALUsr, ReadALUsr]> {
1675 Sched<[WriteALU, ReadALU]>;
1680 Sched<[WriteALU, ReadALU, ReadALU]> {
1688 Sched<[WriteALUsi, ReadALU]>;
1695 Sched<[WriteALUSsr, ReadALUsr]>;
1707 Sched<[WriteALU, ReadALU]>;
1714 Sched<[WriteALUsi, ReadALU]>;
1721 Sched<[WriteALUSsr, ReadALUsr]>;
1736 Sched<[WriteCMP, ReadALU]> {
1750 Sched<[WriteCMP, ReadALU, ReadALU]> {
1768 Sched<[WriteCMPsi, ReadALU]> {
1785 Sched<[WriteCMPsr, ReadALU]> {
1811 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1824 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1837 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1852 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1868 Sched<[WriteALU, ReadALU]> {
1881 Sched<[WriteALU, ReadALU, ReadALU]> {
1897 Sched<[WriteALUsi, ReadALU]> {
1914 Sched<[WriteALUsr, ReadALUsr]> {
1938 Sched<[WriteALU, ReadALU]> {
1950 Sched<[WriteALU, ReadALU, ReadALU]> {
1964 Sched<[WriteALUsi, ReadALU]> {
1979 Sched<[WriteALUsr, ReadALUsr]> {
2269 Sched<[WritePreLd]> {
2286 Sched<[WritePreLd]> {
2369 Sched<[WriteALU, ReadALU]>;
2414 Sched<[WriteALU, ReadALU]> {
2429 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2433 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
2444 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2451 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
2467 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2475 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
2492 Requires<[IsARM]>, Sched<[WriteBrL]> {
2502 Requires<[IsARM]>, Sched<[WriteBrL]> {
2510 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2517 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]>;
2522 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2530 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]>;
2537 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2542 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2548 Requires<[IsARM]>, Sched<[WriteBr]>;
2554 Requires<[IsARM]>, Sched<[WriteBr]>;
2573 Sched<[WriteBr]> {
2588 Sched<[WriteBr]>;
2595 Sched<[WriteBr]>;
2600 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2605 tjumptable:$jt)]>, Sched<[WriteBrTbl]>;
2610 Sched<[WriteBrTbl]>;
2619 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2629 [/* pattern left blank */]>, Sched<[WriteBr]> {
2643 Sched<[WriteBr]>;
2646 Sched<[WriteBr]>;
2651 Requires<[IsARM]>, Sched<[WriteBr]>;
2655 (BX GPR:$dst)>, Sched<[WriteBr]>,
2671 Sched<[WriteBr]> {
3573 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3587 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3601 Sched<[WriteALU]> {
3617 UnaryDP, Sched<[WriteALU]> {
3631 Sched<[WriteALU]> {
3645 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3664 Sched<[WriteALU]>;
3674 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3689 Sched<[WriteALU]>;
3699 Requires<[IsARM]>, Sched<[WriteALU]>;
3707 Sched<[WriteALU]>, Requires<[IsARM]>;
3710 Sched<[WriteALU]>, Requires<[IsARM]>;
3908 Sched<[WriteALU, ReadALU, ReadALU]> {
4027 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
4042 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
4200 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
4214 Sched<[WriteALU]> {
4229 Sched<[WriteALU]> {
4246 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
4306 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
4318 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
4326 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
4338 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4344 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
4364 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
4372 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>;
4382 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
4391 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
4400 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4405 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4412 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
4431 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4438 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4448 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
4456 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
4465 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4472 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4478 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4485 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4492 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4498 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4504 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4510 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4516 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4522 Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
4534 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4542 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4550 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4558 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4566 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4574 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
4589 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4651 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4656 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
4663 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
4670 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
4697 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
4700 Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
4722 Sched<[WriteDIV]>;
4728 Sched<[WriteDIV]>;
4737 Sched<[WriteALU]>;
4743 Sched<[WriteALU]>;
4748 Sched<[WriteALU]>;
4755 Sched<[WriteALU]>;
4769 Sched<[WriteALU]>;
4782 Sched<[WriteALUsi, ReadALU]>;
4799 Sched<[WriteALUsi, ReadALU]>;
4900 Sched<[WriteCMP, ReadALU]> {
4916 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4935 Sched<[WriteCMPsi, ReadALU]> {
4954 Sched<[WriteCMPsr, ReadALU]> {
4994 Sched<[WriteBr]>;
4999 Sched<[WriteBr]>;
5012 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5020 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5026 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5037 Sched<[WriteALU]>;
5045 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5063 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
5139 Requires<[IsARM, HasSB]>, Sched<[]> {
5879 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>,
5955 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5961 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
6432 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
6436 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
6457 NoItinerary, []>, Sched<[]>;
6461 NoItinerary, []>, Sched<[]>;
6465 NoItinerary, []>, Sched<[]>;
6469 NoItinerary, []>, Sched<[]>;
6484 …def SEH_StackAlloc : PseudoInst<(outs), (ins i32imm:$size, i32imm:$wide), NoItinerary, []>, Sched<…
6485 …def SEH_SaveRegs : PseudoInst<(outs), (ins i32imm:$mask, i32imm:$wide), NoItinerary, []>, Sched<[]…
6487 …EH_SaveRegs_Ret : PseudoInst<(outs), (ins i32imm:$mask, i32imm:$wide), NoItinerary, []>, Sched<[]>;
6488 def SEH_SaveSP : PseudoInst<(outs), (ins i32imm:$reg), NoItinerary, []>, Sched<[]>;
6489 …def SEH_SaveFRegs : PseudoInst<(outs), (ins i32imm:$first, i32imm:$last), NoItinerary, []>, Sched<…
6491 def SEH_SaveLR : PseudoInst<(outs), (ins i32imm:$offst), NoItinerary, []>, Sched<[]>;
6492 def SEH_Nop : PseudoInst<(outs), (ins i32imm:$wide), NoItinerary, []>, Sched<[]>;
6494 def SEH_Nop_Ret : PseudoInst<(outs), (ins i32imm:$wide), NoItinerary, []>, Sched<[]>;
6495 def SEH_PrologEnd : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
6496 def SEH_EpilogStart : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
6498 def SEH_EpilogEnd : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;