Lines Matching refs:Sched
689 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> {
708 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
736 Sched<[WriteALU, ReadALU]> {
746 Sched<[WriteALU, ReadALU, ReadALU]> {
771 Sched<[WriteALUsi, ReadALU]> {
833 Sched<[WriteALU, ReadALU]> {
844 Sched<[WriteALU, ReadALU, ReadALU]> {
857 Sched<[WriteALUsi, ReadALU]> {
879 Sched<[WriteALU, ReadALU]>;
885 Sched<[WriteALU, ReadALU, ReadALU]> {
894 Sched<[WriteALUsi, ReadALUsr]>;
908 Sched<[WriteALU, ReadALU]>;
915 Sched<[WriteALUsi, ReadALU]>;
931 Sched<[WriteALU, ReadALU]> {
947 Sched<[WriteALU, ReadALU]> {
960 Sched<[WriteALU, ReadALU]> {
979 Sched<[WriteALU, ReadALU]> {
999 Sched<[WriteALU, ReadALU, ReadALU]> {
1014 Sched<[WriteALUsi, ReadALU]> {
1032 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
1042 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
1056 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
1072 Sched<[WriteALU]> {
1084 Sched<[WriteALU]> {
1128 [(opnode LHSGPR:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
1140 [(opnode LHSGPR:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
1155 Sched<[WriteCMPsi]> {
1180 Sched<[WriteLd]> {
1197 Sched<[WriteLd]> {
1220 Sched<[WriteLd]> {
1245 Sched<[WriteLd]> {
1272 Sched<[WriteST]> {
1290 Sched<[WriteST]> {
1311 Sched<[WriteST]> {
1350 Sched<[WriteALU, ReadALU]>;
1359 Sched<[WriteALU, ReadALU]>;
1368 Sched<[WriteALU, ReadALU]> {
1403 Sched<[WriteALU, ReadALU]> {
1426 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1431 []>, Sched<[WriteALU, ReadALU]>;
1460 Sched<[WriteLd]>;
1515 Sched<[WriteLd]>;
1521 Sched<[WriteLd]>;
1527 Sched<[WriteLd]>;
1533 Sched<[WriteLd]>;
1539 Sched<[WriteLd]>;
1545 Sched<[WriteLd]>;
1551 []>, Sched<[WriteLd]>;
1557 Sched<[WriteLd]>;
1563 []>, Sched<[WriteLd]>;
1569 Sched<[WriteLd]>;
1584 "\t$Rt, $addr", []>, Sched<[WriteLd]> {
1629 Sched<[WriteLd]>;
1632 Sched<[WriteLd]>;
1635 Sched<[WriteLd]>;
1650 Sched<[WriteST]>;
1660 Sched<[WriteST]>;
1667 Sched<[WriteST]>;
1674 Sched<[WriteST]>;
1686 Sched<[WriteST]>;
1697 Sched<[WriteST]>;
1708 Sched<[WriteST]>;
1722 Sched<[WriteST]>;
1728 Sched<[WriteST]>;
1734 Sched<[WriteST]>;
1751 "\t$Rt, $addr", []>, Sched<[WriteST]> {
1778 Sched<[WriteLd]> {
1786 "$addr.base = $wb", []>, Sched<[WriteLd]>;
1792 "$addr.base = $wb", []>, Sched<[WriteST]> {
1801 "$addr.base = $wb", []>, Sched<[WriteST]>;
1807 Sched<[WriteST]> {
1838 Sched<[WritePreLd]> {
1857 Sched<[WritePreLd]> {
1877 Sched<[WritePreLd]> {
1933 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
2130 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
2151 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
2174 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
2195 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>;
2201 Sched<[WriteALU]>;
2209 Sched<[WriteALU]>,
2232 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
2636 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2643 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2651 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2657 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2716 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2733 Sched<[WriteALU]> {
2748 Sched<[WriteALU]> {
2800 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {
2816 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2827 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2855 bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {
2889 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2902 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2915 Sched<[WriteALU]> {
2965 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
2977 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
3016 Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
3034 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
3054 Sched<[WriteMUL16, ReadMUL, ReadMUL]> {
3101 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]> {
3174 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
3205 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
3229 Sched<[WriteDIV]> {
3241 Sched<[WriteDIV]> {
3267 Sched<[WriteALU]>;
3272 Sched<[WriteALU]>;
3276 Sched<[WriteALU]>;
3281 Sched<[WriteALU]>;
3289 Sched<[WriteALU]>;
3302 Sched<[WriteALUsi, ReadALU]> {
3331 Sched<[WriteALUsi, ReadALU]> {
3405 Sched<[WriteCMP, ReadALU]> {
3418 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
3434 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
3473 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3482 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3492 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3502 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3511 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3570 Requires<[IsThumb2, HasSB]>, Sched<[]> {
3613 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>;
3618 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]>;
3623 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteLd]> {
3639 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteLd]> {
3647 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>;
3652 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]>;
3657 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>, Sched<[WriteLd]> {
3673 HasAcquireRelease, HasV7Clrex, IsNotMClass]>, Sched<[WriteLd]> {
3688 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>;
3695 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]>;
3703 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteST]> {
3720 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteST]> {
3731 HasV7Clrex]>, Sched<[WriteST]>;
3740 HasV7Clrex]>, Sched<[WriteST]>;
3749 Sched<[WriteST]> {
3766 HasV7Clrex, IsNotMClass]>, Sched<[WriteST]> {
3864 [(br bb:$target)]>, Sched<[WriteBr]>,
3888 Sched<[WriteBr]>;
3893 Sched<[WriteBr]>;
3897 Sched<[WriteBr]>;
3900 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3913 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3933 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3962 Requires<[IsThumb2]>, Sched<[WriteBr]>;
3986 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
4002 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
4014 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
4215 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
5019 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
5023 : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
5548 4, IIC_Br, []>, Sched<[WriteBr]>;
5557 Sched<[WriteBr]>;
5567 Sched<[WriteBr]>;
5575 Sched<[WriteBr]>;
5580 8, IIC_Br, []>, Sched<[WriteBr]>;
5588 8, IIC_Br, []>, Sched<[WriteBr]>;
5756 Requires<[IsThumb2]>, Sched<[WriteBrL]>;