| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 401 STRICT_FSUB, enumerator
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 260 case ISD::STRICT_FSUB: return "strict_fsub"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 2379 Sub = DAG.getNode(ISD::STRICT_FSUB, dl, {MVT::f64, MVT::Other}, in ExpandLegalINT_TO_FP()
3868 case ISD::STRICT_FSUB: { in ExpandNode()
3870 ISD::STRICT_FSUB, Node->getValueType(0)) == TargetLowering::Legal) in ExpandNode()
4376 case ISD::STRICT_FSUB: in ConvertNodeToLibcall()
4763 case ISD::STRICT_FSUB: in PromoteNode()
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| H A D | LegalizeFloatTypes.cpp | 126 case ISD::STRICT_FSUB: in SoftenFloatResult()
1266 case ISD::STRICT_FSUB: in ExpandFloatResult()
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| H A D | TargetLowering.cpp | 7437 Node->isStrictFPOpcode() ? ISD::STRICT_FSUB : ISD::FSUB, SrcVT)) in expandFP_TO_UINT()
7471 SDValue Val = DAG.getNode(ISD::STRICT_FSUB, dl, { SrcVT, MVT::Other }, in expandFP_TO_UINT()
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| H A D | DAGCombiner.cpp | 14784 if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::STRICT_FSUB, VT)) in visitSTRICT_FADD()
14787 return DAG.getNode(ISD::STRICT_FSUB, DL, DAG.getVTList(VT, ChainVT), in visitSTRICT_FADD()
14792 if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::STRICT_FSUB, VT)) in visitSTRICT_FADD()
14795 return DAG.getNode(ISD::STRICT_FSUB, DL, DAG.getVTList(VT, ChainVT), in visitSTRICT_FADD()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 344 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal); in PPCTargetLowering()
350 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal); in PPCTargetLowering()
1126 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal); in PPCTargetLowering()
1140 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal); in PPCTargetLowering()
1216 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal); in PPCTargetLowering()
8214 SDValue Val = DAG.getNode(ISD::STRICT_FSUB, dl, in LowerFP_TO_INT()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 479 setOperationAction(ISD::STRICT_FSUB, VT, Legal); in SystemZTargetLowering()
528 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal); in SystemZTargetLowering()
585 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal); in SystemZTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 638 setOperationAction(ISD::STRICT_FSUB, MVT::f16, Promote); in X86TargetLowering()
750 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal); in X86TargetLowering()
751 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal); in X86TargetLowering()
803 setOperationAction(ISD::STRICT_FSUB , MVT::f80, Legal); in X86TargetLowering()
828 setOperationAction(ISD::STRICT_FSUB, MVT::f128, LibCall); in X86TargetLowering()
994 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal); in X86TargetLowering()
1204 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal); in X86TargetLowering()
1373 setOperationAction(ISD::STRICT_FSUB, MVT::v8f32, Legal); in X86TargetLowering()
1699 setOperationAction(ISD::STRICT_FSUB, MVT::v16f32, Legal); in X86TargetLowering()
1700 setOperationAction(ISD::STRICT_FSUB, MVT::v8f64, Legal); in X86TargetLowering()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 523 def strict_fsub : SDNode<"ISD::STRICT_FSUB",
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 612 ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV, in AArch64TargetLowering()
695 for (auto Op : {ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL, in AArch64TargetLowering()
961 ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV, in AArch64TargetLowering()
1528 ISD::STRICT_FMAXNUM, ISD::STRICT_FADD, ISD::STRICT_FSUB, in addTypeForNEON()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 307 ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV, in RISCVTargetLowering()
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