| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 476 STRICT_FSETCCS, enumerator
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| H A D | SelectionDAG.h | 1091 return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1036 case ISD::STRICT_FSETCCS: in LegalizeOp()
1043 : Opc == ISD::STRICT_FSETCCS ? 3 in LegalizeOp()
1048 : Opc == ISD::STRICT_FSETCCS ? 1 in LegalizeOp()
3619 case ISD::STRICT_FSETCCS: { in ExpandNode()
3622 Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandNode()
3623 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandNode()
4460 Node->getOpcode() == ISD::STRICT_FSETCCS) in PromoteNode()
4706 case ISD::STRICT_FSETCCS: { in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 1578 Node->getOpcode() == ISD::STRICT_FSETCCS) in UnrollStrictFPOp()
1612 Node->getOpcode() == ISD::STRICT_FSETCCS) in UnrollStrictFPOp()
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| H A D | SelectionDAGDumper.cpp | 286 case ISD::STRICT_FSETCCS: return "strict_fsetccs"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 857 case ISD::STRICT_FSETCCS: in SoftenFloatOperand()
1041 Chain, N->getOpcode() == ISD::STRICT_FSETCCS); in SoftenFloatOp_SETCC()
1807 case ISD::STRICT_FSETCCS: in ExpandFloatOperand()
1978 N->getOpcode() == ISD::STRICT_FSETCCS); in ExpandFloatOp_SETCC()
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| H A D | LegalizeVectorTypes.cpp | 4088 case ISD::STRICT_FSETCCS: in WidenVecRes_StrictFP()
5014 case ISD::STRICT_FSETCCS: in isSETCCOp()
5441 case ISD::STRICT_FSETCCS: Res = WidenVecOp_STRICT_FSETCC(N); break; in WidenVectorOperand()
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| H A D | SelectionDAGISel.cpp | 1137 case ISD::STRICT_FSETCCS: in DoInstructionSelection()
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| H A D | SelectionDAG.cpp | 3265 case ISD::STRICT_FSETCCS: { in computeKnownBits()
4175 case ISD::STRICT_FSETCCS: { in ComputeNumSignBits()
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| H A D | LegalizeIntegerTypes.cpp | 87 case ISD::STRICT_FSETCCS: in PromoteIntegerResult()
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| H A D | DAGCombiner.cpp | 906 N.getOpcode() == ISD::STRICT_FSETCCS)) { in isSetCCEquivalent()
8473 case ISD::STRICT_FSETCCS: { in visitXOR()
8479 N0.getOperand(0), N0Opcode == ISD::STRICT_FSETCCS); in visitXOR()
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| H A D | SelectionDAGBuilder.cpp | 7350 case ISD::STRICT_FSETCCS: { in visitConstrainedFPIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 514 Opcode = ISD::STRICT_FSETCCS; in mightUseCTR()
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| H A D | PPCISelLowering.cpp | 503 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
504 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
505 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal); in PPCTargetLowering()
524 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
525 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
1267 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom); in PPCTargetLowering()
3516 Op->getOpcode() == ISD::STRICT_FSETCCS); in LowerSETCC()
11148 case ISD::STRICT_FSETCCS: in LowerOperation()
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| H A D | PPCISelDAGToDAG.cpp | 5176 case ISD::STRICT_FSETCCS: in Select()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 145 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in SystemZTargetLowering()
403 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in SystemZTargetLowering()
5707 case ISD::STRICT_FSETCCS: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 389 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom); in AArch64TargetLowering()
390 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom); in AArch64TargetLowering()
391 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom); in AArch64TargetLowering()
448 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom); in AArch64TargetLowering()
1551 setOperationAction(ISD::STRICT_FSETCCS, VT, Expand); in addTypeForNEON()
5370 case ISD::STRICT_FSETCCS: in LowerOperation()
8002 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 592 def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>;
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 455 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
658 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Promote); in X86TargetLowering()
1076 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
1426 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
1632 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
1816 setOperationAction(ISD::STRICT_FSETCCS, VT, Custom); in X86TargetLowering()
24274 Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerVSETCC()
24289 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerVSETCC()
24836 Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC()
24909 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1472 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom); in ARMTargetLowering()
1474 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom); in ARMTargetLowering()
1476 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom); in ARMTargetLowering()
10290 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerFSETCC()
10449 case ISD::STRICT_FSETCCS: return LowerFSETCC(Op, DAG); in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 308 ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS}; in RISCVTargetLowering()
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