| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 475 STRICT_FSETCC, enumerator
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| H A D | SelectionDAG.h | 1091 return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1035 case ISD::STRICT_FSETCC: in LegalizeOp()
1042 : Opc == ISD::STRICT_FSETCC ? 3 in LegalizeOp()
1047 : Opc == ISD::STRICT_FSETCC ? 1 in LegalizeOp()
3618 case ISD::STRICT_FSETCC: in ExpandNode()
3621 bool IsStrict = Node->getOpcode() == ISD::STRICT_FSETCC || in ExpandNode()
4459 Node->getOpcode() == ISD::STRICT_FSETCC || in PromoteNode()
4705 case ISD::STRICT_FSETCC: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 1577 if (Node->getOpcode() == ISD::STRICT_FSETCC || in UnrollStrictFPOp()
1611 if (Node->getOpcode() == ISD::STRICT_FSETCC || in UnrollStrictFPOp()
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| H A D | SelectionDAGDumper.cpp | 285 case ISD::STRICT_FSETCC: return "strict_fsetcc"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 856 case ISD::STRICT_FSETCC: in SoftenFloatOperand()
1806 case ISD::STRICT_FSETCC: in ExpandFloatOperand()
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| H A D | LegalizeVectorTypes.cpp | 4087 case ISD::STRICT_FSETCC: in WidenVecRes_StrictFP()
5013 case ISD::STRICT_FSETCC: in isSETCCOp()
5440 case ISD::STRICT_FSETCC: in WidenVectorOperand()
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| H A D | SelectionDAGISel.cpp | 1136 case ISD::STRICT_FSETCC: in DoInstructionSelection()
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| H A D | SelectionDAG.cpp | 3264 case ISD::STRICT_FSETCC: in computeKnownBits()
4174 case ISD::STRICT_FSETCC: in ComputeNumSignBits()
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| H A D | LegalizeIntegerTypes.cpp | 86 case ISD::STRICT_FSETCC: in PromoteIntegerResult()
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| H A D | DAGCombiner.cpp | 905 (N.getOpcode() == ISD::STRICT_FSETCC || in isSetCCEquivalent()
8472 case ISD::STRICT_FSETCC: in visitXOR()
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| H A D | SelectionDAGBuilder.cpp | 7349 case ISD::STRICT_FSETCC: in visitConstrainedFPIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 511 Opcode = ISD::STRICT_FSETCC; in mightUseCTR()
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| H A D | PPCISelLowering.cpp | 499 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal); in PPCTargetLowering()
500 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal); in PPCTargetLowering()
501 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal); in PPCTargetLowering()
1266 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom); in PPCTargetLowering()
11147 case ISD::STRICT_FSETCC: in LowerOperation()
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| H A D | PPCISelDAGToDAG.cpp | 5175 case ISD::STRICT_FSETCC: in Select()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 144 setOperationAction(ISD::STRICT_FSETCC, VT, Custom); in SystemZTargetLowering()
401 setOperationAction(ISD::STRICT_FSETCC, VT, Custom); in SystemZTargetLowering()
5705 case ISD::STRICT_FSETCC: in LowerOperation()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 591 def strict_fsetcc : SDNode<"ISD::STRICT_FSETCC", SDTSetCC, [SDNPHasChain]>;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 386 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom); in AArch64TargetLowering()
387 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom); in AArch64TargetLowering()
388 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom); in AArch64TargetLowering()
447 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom); in AArch64TargetLowering()
1550 setOperationAction(ISD::STRICT_FSETCC, VT, Expand); in addTypeForNEON()
5369 case ISD::STRICT_FSETCC: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 454 setOperationAction(ISD::STRICT_FSETCC, VT, Custom); in X86TargetLowering()
657 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Promote); in X86TargetLowering()
1075 setOperationAction(ISD::STRICT_FSETCC, VT, Custom); in X86TargetLowering()
1425 setOperationAction(ISD::STRICT_FSETCC, VT, Custom); in X86TargetLowering()
1631 setOperationAction(ISD::STRICT_FSETCC, VT, Custom); in X86TargetLowering()
1815 setOperationAction(ISD::STRICT_FSETCC, VT, Custom); in X86TargetLowering()
2078 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom); in X86TargetLowering()
2131 setOperationAction(ISD::STRICT_FSETCC, MVT::v32i1, Custom); in X86TargetLowering()
24273 bool IsStrict = Op.getOpcode() == ISD::STRICT_FSETCC || in LowerVSETCC()
24835 bool IsStrict = Op.getOpcode() == ISD::STRICT_FSETCC || in LowerSETCC()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1471 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom); in ARMTargetLowering()
1473 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom); in ARMTargetLowering()
1475 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom); in ARMTargetLowering()
10448 case ISD::STRICT_FSETCC: in LowerOperation()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 308 ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS}; in RISCVTargetLowering()
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