| /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/ |
| H A D | branch-folder-hoist-livein.mir | 37 … STH renamable $r1l, killed renamable $r3d, 0, $noreg, implicit killed $r4d :: (store (s8) into @d)
43 … STH renamable $r1l, killed renamable $r3d, 0, $noreg, implicit killed $r4d :: (store (s8) into @d)
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| H A D | int-move-05.ll | 34 ; Check the high end of the STH range.
44 ; Check the next halfword up, which should use STHY instead of STH.
108 ; Check that STH allows an index.
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| H A D | cond-store-02.ll | 178 ; Check the high end of the aligned STH range.
194 ; Check the next halfword up, which should use STHY instead of STH.
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| /llvm-project-15.0.7/lld/ELF/Arch/ |
| H A D | PPCInsns.def | 19 PCREL_OPT(STH, PSTH, OPC_AND_RST);
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| H A D | PPC64.cpp | 55 STH = 44, enumerator
85 STH = 0xb0000000, enumerator
840 return STH; in getPPCDFormOp()
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 62 StOpc = BPF::STH; in expandMEMCPY()
101 BuildMI(*BB, MI, dl, get(BPF::STH)) in expandMEMCPY()
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| H A D | BPFMISimplifyPatchable.cpp | 121 Opcode == BPF::LDD || Opcode == BPF::STB || Opcode == BPF::STH || in checkADDrr()
139 if (Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW || in checkADDrr()
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| H A D | BPFInstrInfo.td | 418 def STH : STOREi64<BPF_H, "u16", truncstorei16>;
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | two-address-crash.mir | 87 STH killed %11, 0, killed %3 :: (store (s16) into %ir.P)
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| H A D | convert-rr-to-ri-instrs.mir | 5449 ; CHECK: STH %3, 900, %0
5456 ; CHECK: STH %3, -900, %0
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 70 case PPC::STH: in hasPCRelativeForm()
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| H A D | PPCFastISel.cpp | 635 Opc = Is32BitInt ? PPC::STH : PPC::STH8; in PPCEmitStore()
706 case PPC::STH : Opc = PPC::STHX; break; in PPCEmitStore()
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| H A D | PPCRegisterInfo.cpp | 108 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
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| H A D | P10InstrResources.td | 1817 STH, STH8,
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| H A D | PPCInstrInfo.cpp | 4153 case PPC::STHX: III.ImmOpcode = PPC::STH; break; in instrHasImmForm()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.td | 803 // STH, STHY or STHH, depending on the choice of register.
806 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
813 defm : StoreGR64Pair<STH, STHY, truncstorei16>;
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| H A D | SystemZInstrInfo.cpp | 1402 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH); in expandPostRAPseudo()
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| H A D | SystemZScheduleZ196.td | 242 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
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| H A D | SystemZScheduleZEC12.td | 253 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
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| H A D | SystemZScheduleZ13.td | 279 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
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| H A D | SystemZScheduleZ16.td | 284 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
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| H A D | SystemZScheduleZ15.td | 284 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
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| H A D | SystemZScheduleZ14.td | 280 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
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| H A D | SystemZISelLowering.cpp | 8793 return emitCondStore(MI, MBB, SystemZ::STH, 0, false); in EmitInstrWithCustomInserter()
8795 return emitCondStore(MI, MBB, SystemZ::STH, 0, true); in EmitInstrWithCustomInserter()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.td | 629 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
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