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Searched refs:SRLI (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dpass-fast-math-flags-sdnode.ll16 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gprnox0 = SRLI killed [[SLLI]], 32
19 …xcept PseudoVFMUL_VV_M1_MASK [[DEF]], [[COPY3]], [[COPY2]], $v0, killed [[SRLI]], 6 /* e64 */, 1, …
H A Dvsetvli-insert-crossbb.mir594 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
605 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]]
618 %2:gpr = SRLI %1:gpr, 3
662 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
673 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]]
690 %2:gpr = SRLI %1:gpr, 3
921 ; CHECK-NEXT: %inc:gpr = SRLI killed %vlenb, 3
970 %inc:gpr = SRLI killed %vlenb, 3
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp25 case RISCV::SRLI: in getInstSeqCost()
213 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, LeadingZeros)); in generateInstSeq()
227 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, LeadingZeros)); in generateInstSeq()
413 case RISCV::SRLI: in getOpndKind()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp705 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
706 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
708 ReplaceNode(Node, SRLI); in Select()
823 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
826 ReplaceNode(Node, SRLI); in Select()
852 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
855 ReplaceNode(Node, SRLI); in Select()
867 unsigned SrliOpc = RISCV::SRLI; in Select()
874 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
903 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
[all …]
H A DRISCVSExtWRemoval.cpp250 case RISCV::SRLI: in isSignExtendingOpW()
H A DRISCVInstrInfo.td640 def SRLI : Shift_ri<0b00000, 0b101, "srli">;
994 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1188 def : PatGprUimmLog2XLen<srl, SRLI>;
1193 (SLLI (SRLI $rs, LeadingOnesMask:$mask), LeadingOnesMask:$mask)>;
1195 (SRLI (SLLI $rs, TrailingOnesMask:$mask), TrailingOnesMask:$mask)>;
1572 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (SLLI GPR:$rs1, 32), 32)>;
1577 (SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
H A DRISCVInstrInfoZb.td1198 // Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
1200 (SH1ADD_UW (SRLI GPR:$rs1, 1), GPR:$rs2)>;
1202 (SH2ADD_UW (SRLI GPR:$rs1, 2), GPR:$rs2)>;
1204 (SH3ADD_UW (SRLI GPR:$rs1, 3), GPR:$rs2)>;
H A DRISCVFrameLowering.cpp571 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR) in emitPrologue()
H A DRISCVInstrInfoC.td805 def : CompressPat<(SRLI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dand.ll75 ; with the remainder zero, we can replace it with SRLI + SLLI.
H A Dimm.ll260 ; This can be materialized with ADDI+SRLI, improving compressibility.
295 ; This can be materialized with LUI+SRLI, improving compressibility.
883 ; This constant can be materialized for RV64 with LUI+SRLI+XORI.
/llvm-project-15.0.7/lld/ELF/Arch/
H A DRISCV.cpp54 SRLI = 0x5013, enumerator
214 write32le(buf + 20, itype(SRLI, X_T1, X_T1, config->is64 ? 1 : 2)); in writePltHeader()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td438 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
H A DMipsScheduleGeneric.td1559 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp2466 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp5569 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { in visitANDLike() local
5575 APInt SRLC = SRLI->getAPIntValue(); in visitANDLike()