1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32I 4; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV64I 6; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zba \ 7; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBA 8; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zbb \ 9; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBB 10; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+zbs \ 11; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBS 12 13; Materializing constants 14 15; TODO: It would be preferable if anyext constant returns were sign rather 16; than zero extended. See PR39092. For now, mark returns as explicitly signext 17; (this matches what Clang would generate for equivalent C/C++ anyway). 18 19define signext i32 @zero() nounwind { 20; RV32I-LABEL: zero: 21; RV32I: # %bb.0: 22; RV32I-NEXT: li a0, 0 23; RV32I-NEXT: ret 24; 25; RV64I-LABEL: zero: 26; RV64I: # %bb.0: 27; RV64I-NEXT: li a0, 0 28; RV64I-NEXT: ret 29; 30; RV64IZBA-LABEL: zero: 31; RV64IZBA: # %bb.0: 32; RV64IZBA-NEXT: li a0, 0 33; RV64IZBA-NEXT: ret 34; 35; RV64IZBB-LABEL: zero: 36; RV64IZBB: # %bb.0: 37; RV64IZBB-NEXT: li a0, 0 38; RV64IZBB-NEXT: ret 39; 40; RV64IZBS-LABEL: zero: 41; RV64IZBS: # %bb.0: 42; RV64IZBS-NEXT: li a0, 0 43; RV64IZBS-NEXT: ret 44 ret i32 0 45} 46 47define signext i32 @pos_small() nounwind { 48; RV32I-LABEL: pos_small: 49; RV32I: # %bb.0: 50; RV32I-NEXT: li a0, 2047 51; RV32I-NEXT: ret 52; 53; RV64I-LABEL: pos_small: 54; RV64I: # %bb.0: 55; RV64I-NEXT: li a0, 2047 56; RV64I-NEXT: ret 57; 58; RV64IZBA-LABEL: pos_small: 59; RV64IZBA: # %bb.0: 60; RV64IZBA-NEXT: li a0, 2047 61; RV64IZBA-NEXT: ret 62; 63; RV64IZBB-LABEL: pos_small: 64; RV64IZBB: # %bb.0: 65; RV64IZBB-NEXT: li a0, 2047 66; RV64IZBB-NEXT: ret 67; 68; RV64IZBS-LABEL: pos_small: 69; RV64IZBS: # %bb.0: 70; RV64IZBS-NEXT: li a0, 2047 71; RV64IZBS-NEXT: ret 72 ret i32 2047 73} 74 75define signext i32 @neg_small() nounwind { 76; RV32I-LABEL: neg_small: 77; RV32I: # %bb.0: 78; RV32I-NEXT: li a0, -2048 79; RV32I-NEXT: ret 80; 81; RV64I-LABEL: neg_small: 82; RV64I: # %bb.0: 83; RV64I-NEXT: li a0, -2048 84; RV64I-NEXT: ret 85; 86; RV64IZBA-LABEL: neg_small: 87; RV64IZBA: # %bb.0: 88; RV64IZBA-NEXT: li a0, -2048 89; RV64IZBA-NEXT: ret 90; 91; RV64IZBB-LABEL: neg_small: 92; RV64IZBB: # %bb.0: 93; RV64IZBB-NEXT: li a0, -2048 94; RV64IZBB-NEXT: ret 95; 96; RV64IZBS-LABEL: neg_small: 97; RV64IZBS: # %bb.0: 98; RV64IZBS-NEXT: li a0, -2048 99; RV64IZBS-NEXT: ret 100 ret i32 -2048 101} 102 103define signext i32 @pos_i32() nounwind { 104; RV32I-LABEL: pos_i32: 105; RV32I: # %bb.0: 106; RV32I-NEXT: lui a0, 423811 107; RV32I-NEXT: addi a0, a0, -1297 108; RV32I-NEXT: ret 109; 110; RV64I-LABEL: pos_i32: 111; RV64I: # %bb.0: 112; RV64I-NEXT: lui a0, 423811 113; RV64I-NEXT: addiw a0, a0, -1297 114; RV64I-NEXT: ret 115; 116; RV64IZBA-LABEL: pos_i32: 117; RV64IZBA: # %bb.0: 118; RV64IZBA-NEXT: lui a0, 423811 119; RV64IZBA-NEXT: addiw a0, a0, -1297 120; RV64IZBA-NEXT: ret 121; 122; RV64IZBB-LABEL: pos_i32: 123; RV64IZBB: # %bb.0: 124; RV64IZBB-NEXT: lui a0, 423811 125; RV64IZBB-NEXT: addiw a0, a0, -1297 126; RV64IZBB-NEXT: ret 127; 128; RV64IZBS-LABEL: pos_i32: 129; RV64IZBS: # %bb.0: 130; RV64IZBS-NEXT: lui a0, 423811 131; RV64IZBS-NEXT: addiw a0, a0, -1297 132; RV64IZBS-NEXT: ret 133 ret i32 1735928559 134} 135 136define signext i32 @neg_i32() nounwind { 137; RV32I-LABEL: neg_i32: 138; RV32I: # %bb.0: 139; RV32I-NEXT: lui a0, 912092 140; RV32I-NEXT: addi a0, a0, -273 141; RV32I-NEXT: ret 142; 143; RV64I-LABEL: neg_i32: 144; RV64I: # %bb.0: 145; RV64I-NEXT: lui a0, 912092 146; RV64I-NEXT: addiw a0, a0, -273 147; RV64I-NEXT: ret 148; 149; RV64IZBA-LABEL: neg_i32: 150; RV64IZBA: # %bb.0: 151; RV64IZBA-NEXT: lui a0, 912092 152; RV64IZBA-NEXT: addiw a0, a0, -273 153; RV64IZBA-NEXT: ret 154; 155; RV64IZBB-LABEL: neg_i32: 156; RV64IZBB: # %bb.0: 157; RV64IZBB-NEXT: lui a0, 912092 158; RV64IZBB-NEXT: addiw a0, a0, -273 159; RV64IZBB-NEXT: ret 160; 161; RV64IZBS-LABEL: neg_i32: 162; RV64IZBS: # %bb.0: 163; RV64IZBS-NEXT: lui a0, 912092 164; RV64IZBS-NEXT: addiw a0, a0, -273 165; RV64IZBS-NEXT: ret 166 ret i32 -559038737 167} 168 169define signext i32 @pos_i32_hi20_only() nounwind { 170; RV32I-LABEL: pos_i32_hi20_only: 171; RV32I: # %bb.0: 172; RV32I-NEXT: lui a0, 16 173; RV32I-NEXT: ret 174; 175; RV64I-LABEL: pos_i32_hi20_only: 176; RV64I: # %bb.0: 177; RV64I-NEXT: lui a0, 16 178; RV64I-NEXT: ret 179; 180; RV64IZBA-LABEL: pos_i32_hi20_only: 181; RV64IZBA: # %bb.0: 182; RV64IZBA-NEXT: lui a0, 16 183; RV64IZBA-NEXT: ret 184; 185; RV64IZBB-LABEL: pos_i32_hi20_only: 186; RV64IZBB: # %bb.0: 187; RV64IZBB-NEXT: lui a0, 16 188; RV64IZBB-NEXT: ret 189; 190; RV64IZBS-LABEL: pos_i32_hi20_only: 191; RV64IZBS: # %bb.0: 192; RV64IZBS-NEXT: lui a0, 16 193; RV64IZBS-NEXT: ret 194 ret i32 65536 ; 0x10000 195} 196 197define signext i32 @neg_i32_hi20_only() nounwind { 198; RV32I-LABEL: neg_i32_hi20_only: 199; RV32I: # %bb.0: 200; RV32I-NEXT: lui a0, 1048560 201; RV32I-NEXT: ret 202; 203; RV64I-LABEL: neg_i32_hi20_only: 204; RV64I: # %bb.0: 205; RV64I-NEXT: lui a0, 1048560 206; RV64I-NEXT: ret 207; 208; RV64IZBA-LABEL: neg_i32_hi20_only: 209; RV64IZBA: # %bb.0: 210; RV64IZBA-NEXT: lui a0, 1048560 211; RV64IZBA-NEXT: ret 212; 213; RV64IZBB-LABEL: neg_i32_hi20_only: 214; RV64IZBB: # %bb.0: 215; RV64IZBB-NEXT: lui a0, 1048560 216; RV64IZBB-NEXT: ret 217; 218; RV64IZBS-LABEL: neg_i32_hi20_only: 219; RV64IZBS: # %bb.0: 220; RV64IZBS-NEXT: lui a0, 1048560 221; RV64IZBS-NEXT: ret 222 ret i32 -65536 ; -0x10000 223} 224 225; This can be materialized with ADDI+SLLI, improving compressibility. 226 227define signext i32 @imm_left_shifted_addi() nounwind { 228; RV32I-LABEL: imm_left_shifted_addi: 229; RV32I: # %bb.0: 230; RV32I-NEXT: lui a0, 32 231; RV32I-NEXT: addi a0, a0, -64 232; RV32I-NEXT: ret 233; 234; RV64I-LABEL: imm_left_shifted_addi: 235; RV64I: # %bb.0: 236; RV64I-NEXT: lui a0, 32 237; RV64I-NEXT: addiw a0, a0, -64 238; RV64I-NEXT: ret 239; 240; RV64IZBA-LABEL: imm_left_shifted_addi: 241; RV64IZBA: # %bb.0: 242; RV64IZBA-NEXT: lui a0, 32 243; RV64IZBA-NEXT: addiw a0, a0, -64 244; RV64IZBA-NEXT: ret 245; 246; RV64IZBB-LABEL: imm_left_shifted_addi: 247; RV64IZBB: # %bb.0: 248; RV64IZBB-NEXT: lui a0, 32 249; RV64IZBB-NEXT: addiw a0, a0, -64 250; RV64IZBB-NEXT: ret 251; 252; RV64IZBS-LABEL: imm_left_shifted_addi: 253; RV64IZBS: # %bb.0: 254; RV64IZBS-NEXT: lui a0, 32 255; RV64IZBS-NEXT: addiw a0, a0, -64 256; RV64IZBS-NEXT: ret 257 ret i32 131008 ; 0x1FFC0 258} 259 260; This can be materialized with ADDI+SRLI, improving compressibility. 261 262define signext i32 @imm_right_shifted_addi() nounwind { 263; RV32I-LABEL: imm_right_shifted_addi: 264; RV32I: # %bb.0: 265; RV32I-NEXT: lui a0, 524288 266; RV32I-NEXT: addi a0, a0, -1 267; RV32I-NEXT: ret 268; 269; RV64I-LABEL: imm_right_shifted_addi: 270; RV64I: # %bb.0: 271; RV64I-NEXT: lui a0, 524288 272; RV64I-NEXT: addiw a0, a0, -1 273; RV64I-NEXT: ret 274; 275; RV64IZBA-LABEL: imm_right_shifted_addi: 276; RV64IZBA: # %bb.0: 277; RV64IZBA-NEXT: lui a0, 524288 278; RV64IZBA-NEXT: addiw a0, a0, -1 279; RV64IZBA-NEXT: ret 280; 281; RV64IZBB-LABEL: imm_right_shifted_addi: 282; RV64IZBB: # %bb.0: 283; RV64IZBB-NEXT: lui a0, 524288 284; RV64IZBB-NEXT: addiw a0, a0, -1 285; RV64IZBB-NEXT: ret 286; 287; RV64IZBS-LABEL: imm_right_shifted_addi: 288; RV64IZBS: # %bb.0: 289; RV64IZBS-NEXT: lui a0, 524288 290; RV64IZBS-NEXT: addiw a0, a0, -1 291; RV64IZBS-NEXT: ret 292 ret i32 2147483647 ; 0x7FFFFFFF 293} 294 295; This can be materialized with LUI+SRLI, improving compressibility. 296 297define signext i32 @imm_right_shifted_lui() nounwind { 298; RV32I-LABEL: imm_right_shifted_lui: 299; RV32I: # %bb.0: 300; RV32I-NEXT: lui a0, 56 301; RV32I-NEXT: addi a0, a0, 580 302; RV32I-NEXT: ret 303; 304; RV64I-LABEL: imm_right_shifted_lui: 305; RV64I: # %bb.0: 306; RV64I-NEXT: lui a0, 56 307; RV64I-NEXT: addiw a0, a0, 580 308; RV64I-NEXT: ret 309; 310; RV64IZBA-LABEL: imm_right_shifted_lui: 311; RV64IZBA: # %bb.0: 312; RV64IZBA-NEXT: lui a0, 56 313; RV64IZBA-NEXT: addiw a0, a0, 580 314; RV64IZBA-NEXT: ret 315; 316; RV64IZBB-LABEL: imm_right_shifted_lui: 317; RV64IZBB: # %bb.0: 318; RV64IZBB-NEXT: lui a0, 56 319; RV64IZBB-NEXT: addiw a0, a0, 580 320; RV64IZBB-NEXT: ret 321; 322; RV64IZBS-LABEL: imm_right_shifted_lui: 323; RV64IZBS: # %bb.0: 324; RV64IZBS-NEXT: lui a0, 56 325; RV64IZBS-NEXT: addiw a0, a0, 580 326; RV64IZBS-NEXT: ret 327 ret i32 229956 ; 0x38244 328} 329 330define i64 @imm64_1() nounwind { 331; RV32I-LABEL: imm64_1: 332; RV32I: # %bb.0: 333; RV32I-NEXT: lui a0, 524288 334; RV32I-NEXT: li a1, 0 335; RV32I-NEXT: ret 336; 337; RV64I-LABEL: imm64_1: 338; RV64I: # %bb.0: 339; RV64I-NEXT: li a0, 1 340; RV64I-NEXT: slli a0, a0, 31 341; RV64I-NEXT: ret 342; 343; RV64IZBA-LABEL: imm64_1: 344; RV64IZBA: # %bb.0: 345; RV64IZBA-NEXT: li a0, 1 346; RV64IZBA-NEXT: slli a0, a0, 31 347; RV64IZBA-NEXT: ret 348; 349; RV64IZBB-LABEL: imm64_1: 350; RV64IZBB: # %bb.0: 351; RV64IZBB-NEXT: li a0, 1 352; RV64IZBB-NEXT: slli a0, a0, 31 353; RV64IZBB-NEXT: ret 354; 355; RV64IZBS-LABEL: imm64_1: 356; RV64IZBS: # %bb.0: 357; RV64IZBS-NEXT: bseti a0, zero, 31 358; RV64IZBS-NEXT: ret 359 ret i64 2147483648 ; 0x8000_0000 360} 361 362define i64 @imm64_2() nounwind { 363; RV32I-LABEL: imm64_2: 364; RV32I: # %bb.0: 365; RV32I-NEXT: li a0, -1 366; RV32I-NEXT: li a1, 0 367; RV32I-NEXT: ret 368; 369; RV64I-LABEL: imm64_2: 370; RV64I: # %bb.0: 371; RV64I-NEXT: li a0, -1 372; RV64I-NEXT: srli a0, a0, 32 373; RV64I-NEXT: ret 374; 375; RV64IZBA-LABEL: imm64_2: 376; RV64IZBA: # %bb.0: 377; RV64IZBA-NEXT: li a0, -1 378; RV64IZBA-NEXT: srli a0, a0, 32 379; RV64IZBA-NEXT: ret 380; 381; RV64IZBB-LABEL: imm64_2: 382; RV64IZBB: # %bb.0: 383; RV64IZBB-NEXT: li a0, -1 384; RV64IZBB-NEXT: srli a0, a0, 32 385; RV64IZBB-NEXT: ret 386; 387; RV64IZBS-LABEL: imm64_2: 388; RV64IZBS: # %bb.0: 389; RV64IZBS-NEXT: li a0, -1 390; RV64IZBS-NEXT: srli a0, a0, 32 391; RV64IZBS-NEXT: ret 392 ret i64 4294967295 ; 0xFFFF_FFFF 393} 394 395define i64 @imm64_3() nounwind { 396; RV32I-LABEL: imm64_3: 397; RV32I: # %bb.0: 398; RV32I-NEXT: li a1, 1 399; RV32I-NEXT: li a0, 0 400; RV32I-NEXT: ret 401; 402; RV64I-LABEL: imm64_3: 403; RV64I: # %bb.0: 404; RV64I-NEXT: li a0, 1 405; RV64I-NEXT: slli a0, a0, 32 406; RV64I-NEXT: ret 407; 408; RV64IZBA-LABEL: imm64_3: 409; RV64IZBA: # %bb.0: 410; RV64IZBA-NEXT: li a0, 1 411; RV64IZBA-NEXT: slli a0, a0, 32 412; RV64IZBA-NEXT: ret 413; 414; RV64IZBB-LABEL: imm64_3: 415; RV64IZBB: # %bb.0: 416; RV64IZBB-NEXT: li a0, 1 417; RV64IZBB-NEXT: slli a0, a0, 32 418; RV64IZBB-NEXT: ret 419; 420; RV64IZBS-LABEL: imm64_3: 421; RV64IZBS: # %bb.0: 422; RV64IZBS-NEXT: bseti a0, zero, 32 423; RV64IZBS-NEXT: ret 424 ret i64 4294967296 ; 0x1_0000_0000 425} 426 427define i64 @imm64_4() nounwind { 428; RV32I-LABEL: imm64_4: 429; RV32I: # %bb.0: 430; RV32I-NEXT: lui a1, 524288 431; RV32I-NEXT: li a0, 0 432; RV32I-NEXT: ret 433; 434; RV64I-LABEL: imm64_4: 435; RV64I: # %bb.0: 436; RV64I-NEXT: li a0, -1 437; RV64I-NEXT: slli a0, a0, 63 438; RV64I-NEXT: ret 439; 440; RV64IZBA-LABEL: imm64_4: 441; RV64IZBA: # %bb.0: 442; RV64IZBA-NEXT: li a0, -1 443; RV64IZBA-NEXT: slli a0, a0, 63 444; RV64IZBA-NEXT: ret 445; 446; RV64IZBB-LABEL: imm64_4: 447; RV64IZBB: # %bb.0: 448; RV64IZBB-NEXT: li a0, -1 449; RV64IZBB-NEXT: slli a0, a0, 63 450; RV64IZBB-NEXT: ret 451; 452; RV64IZBS-LABEL: imm64_4: 453; RV64IZBS: # %bb.0: 454; RV64IZBS-NEXT: bseti a0, zero, 63 455; RV64IZBS-NEXT: ret 456 ret i64 9223372036854775808 ; 0x8000_0000_0000_0000 457} 458 459define i64 @imm64_5() nounwind { 460; RV32I-LABEL: imm64_5: 461; RV32I: # %bb.0: 462; RV32I-NEXT: lui a1, 524288 463; RV32I-NEXT: li a0, 0 464; RV32I-NEXT: ret 465; 466; RV64I-LABEL: imm64_5: 467; RV64I: # %bb.0: 468; RV64I-NEXT: li a0, -1 469; RV64I-NEXT: slli a0, a0, 63 470; RV64I-NEXT: ret 471; 472; RV64IZBA-LABEL: imm64_5: 473; RV64IZBA: # %bb.0: 474; RV64IZBA-NEXT: li a0, -1 475; RV64IZBA-NEXT: slli a0, a0, 63 476; RV64IZBA-NEXT: ret 477; 478; RV64IZBB-LABEL: imm64_5: 479; RV64IZBB: # %bb.0: 480; RV64IZBB-NEXT: li a0, -1 481; RV64IZBB-NEXT: slli a0, a0, 63 482; RV64IZBB-NEXT: ret 483; 484; RV64IZBS-LABEL: imm64_5: 485; RV64IZBS: # %bb.0: 486; RV64IZBS-NEXT: bseti a0, zero, 63 487; RV64IZBS-NEXT: ret 488 ret i64 -9223372036854775808 ; 0x8000_0000_0000_0000 489} 490 491define i64 @imm64_6() nounwind { 492; RV32I-LABEL: imm64_6: 493; RV32I: # %bb.0: 494; RV32I-NEXT: lui a0, 74565 495; RV32I-NEXT: addi a1, a0, 1656 496; RV32I-NEXT: li a0, 0 497; RV32I-NEXT: ret 498; 499; RV64I-LABEL: imm64_6: 500; RV64I: # %bb.0: 501; RV64I-NEXT: lui a0, 9321 502; RV64I-NEXT: addiw a0, a0, -1329 503; RV64I-NEXT: slli a0, a0, 35 504; RV64I-NEXT: ret 505; 506; RV64IZBA-LABEL: imm64_6: 507; RV64IZBA: # %bb.0: 508; RV64IZBA-NEXT: lui a0, 9321 509; RV64IZBA-NEXT: addiw a0, a0, -1329 510; RV64IZBA-NEXT: slli a0, a0, 35 511; RV64IZBA-NEXT: ret 512; 513; RV64IZBB-LABEL: imm64_6: 514; RV64IZBB: # %bb.0: 515; RV64IZBB-NEXT: lui a0, 9321 516; RV64IZBB-NEXT: addiw a0, a0, -1329 517; RV64IZBB-NEXT: slli a0, a0, 35 518; RV64IZBB-NEXT: ret 519; 520; RV64IZBS-LABEL: imm64_6: 521; RV64IZBS: # %bb.0: 522; RV64IZBS-NEXT: lui a0, 9321 523; RV64IZBS-NEXT: addiw a0, a0, -1329 524; RV64IZBS-NEXT: slli a0, a0, 35 525; RV64IZBS-NEXT: ret 526 ret i64 1311768464867721216 ; 0x1234_5678_0000_0000 527} 528 529define i64 @imm64_7() nounwind { 530; RV32I-LABEL: imm64_7: 531; RV32I: # %bb.0: 532; RV32I-NEXT: lui a0, 45056 533; RV32I-NEXT: addi a0, a0, 15 534; RV32I-NEXT: lui a1, 458752 535; RV32I-NEXT: ret 536; 537; RV64I-LABEL: imm64_7: 538; RV64I: # %bb.0: 539; RV64I-NEXT: li a0, 7 540; RV64I-NEXT: slli a0, a0, 36 541; RV64I-NEXT: addi a0, a0, 11 542; RV64I-NEXT: slli a0, a0, 24 543; RV64I-NEXT: addi a0, a0, 15 544; RV64I-NEXT: ret 545; 546; RV64IZBA-LABEL: imm64_7: 547; RV64IZBA: # %bb.0: 548; RV64IZBA-NEXT: li a0, 7 549; RV64IZBA-NEXT: slli a0, a0, 36 550; RV64IZBA-NEXT: addi a0, a0, 11 551; RV64IZBA-NEXT: slli a0, a0, 24 552; RV64IZBA-NEXT: addi a0, a0, 15 553; RV64IZBA-NEXT: ret 554; 555; RV64IZBB-LABEL: imm64_7: 556; RV64IZBB: # %bb.0: 557; RV64IZBB-NEXT: li a0, 7 558; RV64IZBB-NEXT: slli a0, a0, 36 559; RV64IZBB-NEXT: addi a0, a0, 11 560; RV64IZBB-NEXT: slli a0, a0, 24 561; RV64IZBB-NEXT: addi a0, a0, 15 562; RV64IZBB-NEXT: ret 563; 564; RV64IZBS-LABEL: imm64_7: 565; RV64IZBS: # %bb.0: 566; RV64IZBS-NEXT: li a0, 7 567; RV64IZBS-NEXT: slli a0, a0, 36 568; RV64IZBS-NEXT: addi a0, a0, 11 569; RV64IZBS-NEXT: slli a0, a0, 24 570; RV64IZBS-NEXT: addi a0, a0, 15 571; RV64IZBS-NEXT: ret 572 ret i64 8070450532432478223 ; 0x7000_0000_0B00_000F 573} 574 575; TODO: it can be preferable to put constants that are expensive to materialise 576; into the constant pool, especially for -Os. 577define i64 @imm64_8() nounwind { 578; RV32I-LABEL: imm64_8: 579; RV32I: # %bb.0: 580; RV32I-NEXT: lui a0, 633806 581; RV32I-NEXT: addi a0, a0, -272 582; RV32I-NEXT: lui a1, 74565 583; RV32I-NEXT: addi a1, a1, 1656 584; RV32I-NEXT: ret 585; 586; RV64I-LABEL: imm64_8: 587; RV64I: # %bb.0: 588; RV64I-NEXT: lui a0, 583 589; RV64I-NEXT: addiw a0, a0, -1875 590; RV64I-NEXT: slli a0, a0, 14 591; RV64I-NEXT: addi a0, a0, -947 592; RV64I-NEXT: slli a0, a0, 12 593; RV64I-NEXT: addi a0, a0, 1511 594; RV64I-NEXT: slli a0, a0, 13 595; RV64I-NEXT: addi a0, a0, -272 596; RV64I-NEXT: ret 597; 598; RV64IZBA-LABEL: imm64_8: 599; RV64IZBA: # %bb.0: 600; RV64IZBA-NEXT: lui a0, 596523 601; RV64IZBA-NEXT: addiw a0, a0, 965 602; RV64IZBA-NEXT: slli.uw a0, a0, 13 603; RV64IZBA-NEXT: addi a0, a0, -1347 604; RV64IZBA-NEXT: slli a0, a0, 12 605; RV64IZBA-NEXT: addi a0, a0, -529 606; RV64IZBA-NEXT: slli a0, a0, 4 607; RV64IZBA-NEXT: ret 608; 609; RV64IZBB-LABEL: imm64_8: 610; RV64IZBB: # %bb.0: 611; RV64IZBB-NEXT: lui a0, 583 612; RV64IZBB-NEXT: addiw a0, a0, -1875 613; RV64IZBB-NEXT: slli a0, a0, 14 614; RV64IZBB-NEXT: addi a0, a0, -947 615; RV64IZBB-NEXT: slli a0, a0, 12 616; RV64IZBB-NEXT: addi a0, a0, 1511 617; RV64IZBB-NEXT: slli a0, a0, 13 618; RV64IZBB-NEXT: addi a0, a0, -272 619; RV64IZBB-NEXT: ret 620; 621; RV64IZBS-LABEL: imm64_8: 622; RV64IZBS: # %bb.0: 623; RV64IZBS-NEXT: lui a0, 583 624; RV64IZBS-NEXT: addiw a0, a0, -1875 625; RV64IZBS-NEXT: slli a0, a0, 14 626; RV64IZBS-NEXT: addi a0, a0, -947 627; RV64IZBS-NEXT: slli a0, a0, 12 628; RV64IZBS-NEXT: addi a0, a0, 1511 629; RV64IZBS-NEXT: slli a0, a0, 13 630; RV64IZBS-NEXT: addi a0, a0, -272 631; RV64IZBS-NEXT: ret 632 ret i64 1311768467463790320 ; 0x1234_5678_9ABC_DEF0 633} 634 635define i64 @imm64_9() nounwind { 636; RV32I-LABEL: imm64_9: 637; RV32I: # %bb.0: 638; RV32I-NEXT: li a0, -1 639; RV32I-NEXT: li a1, -1 640; RV32I-NEXT: ret 641; 642; RV64I-LABEL: imm64_9: 643; RV64I: # %bb.0: 644; RV64I-NEXT: li a0, -1 645; RV64I-NEXT: ret 646; 647; RV64IZBA-LABEL: imm64_9: 648; RV64IZBA: # %bb.0: 649; RV64IZBA-NEXT: li a0, -1 650; RV64IZBA-NEXT: ret 651; 652; RV64IZBB-LABEL: imm64_9: 653; RV64IZBB: # %bb.0: 654; RV64IZBB-NEXT: li a0, -1 655; RV64IZBB-NEXT: ret 656; 657; RV64IZBS-LABEL: imm64_9: 658; RV64IZBS: # %bb.0: 659; RV64IZBS-NEXT: li a0, -1 660; RV64IZBS-NEXT: ret 661 ret i64 -1 662} 663 664; Various cases where extraneous ADDIs can be inserted where a (left shifted) 665; LUI suffices. 666 667define i64 @imm_left_shifted_lui_1() nounwind { 668; RV32I-LABEL: imm_left_shifted_lui_1: 669; RV32I: # %bb.0: 670; RV32I-NEXT: lui a0, 524290 671; RV32I-NEXT: li a1, 0 672; RV32I-NEXT: ret 673; 674; RV64I-LABEL: imm_left_shifted_lui_1: 675; RV64I: # %bb.0: 676; RV64I-NEXT: lui a0, 262145 677; RV64I-NEXT: slli a0, a0, 1 678; RV64I-NEXT: ret 679; 680; RV64IZBA-LABEL: imm_left_shifted_lui_1: 681; RV64IZBA: # %bb.0: 682; RV64IZBA-NEXT: lui a0, 262145 683; RV64IZBA-NEXT: slli a0, a0, 1 684; RV64IZBA-NEXT: ret 685; 686; RV64IZBB-LABEL: imm_left_shifted_lui_1: 687; RV64IZBB: # %bb.0: 688; RV64IZBB-NEXT: lui a0, 262145 689; RV64IZBB-NEXT: slli a0, a0, 1 690; RV64IZBB-NEXT: ret 691; 692; RV64IZBS-LABEL: imm_left_shifted_lui_1: 693; RV64IZBS: # %bb.0: 694; RV64IZBS-NEXT: lui a0, 262145 695; RV64IZBS-NEXT: slli a0, a0, 1 696; RV64IZBS-NEXT: ret 697 ret i64 2147491840 ; 0x8000_2000 698} 699 700define i64 @imm_left_shifted_lui_2() nounwind { 701; RV32I-LABEL: imm_left_shifted_lui_2: 702; RV32I: # %bb.0: 703; RV32I-NEXT: lui a0, 4 704; RV32I-NEXT: li a1, 1 705; RV32I-NEXT: ret 706; 707; RV64I-LABEL: imm_left_shifted_lui_2: 708; RV64I: # %bb.0: 709; RV64I-NEXT: lui a0, 262145 710; RV64I-NEXT: slli a0, a0, 2 711; RV64I-NEXT: ret 712; 713; RV64IZBA-LABEL: imm_left_shifted_lui_2: 714; RV64IZBA: # %bb.0: 715; RV64IZBA-NEXT: lui a0, 262145 716; RV64IZBA-NEXT: slli a0, a0, 2 717; RV64IZBA-NEXT: ret 718; 719; RV64IZBB-LABEL: imm_left_shifted_lui_2: 720; RV64IZBB: # %bb.0: 721; RV64IZBB-NEXT: lui a0, 262145 722; RV64IZBB-NEXT: slli a0, a0, 2 723; RV64IZBB-NEXT: ret 724; 725; RV64IZBS-LABEL: imm_left_shifted_lui_2: 726; RV64IZBS: # %bb.0: 727; RV64IZBS-NEXT: lui a0, 262145 728; RV64IZBS-NEXT: slli a0, a0, 2 729; RV64IZBS-NEXT: ret 730 ret i64 4294983680 ; 0x1_0000_4000 731} 732 733define i64 @imm_left_shifted_lui_3() nounwind { 734; RV32I-LABEL: imm_left_shifted_lui_3: 735; RV32I: # %bb.0: 736; RV32I-NEXT: lui a0, 1 737; RV32I-NEXT: addi a1, a0, 1 738; RV32I-NEXT: li a0, 0 739; RV32I-NEXT: ret 740; 741; RV64I-LABEL: imm_left_shifted_lui_3: 742; RV64I: # %bb.0: 743; RV64I-NEXT: lui a0, 4097 744; RV64I-NEXT: slli a0, a0, 20 745; RV64I-NEXT: ret 746; 747; RV64IZBA-LABEL: imm_left_shifted_lui_3: 748; RV64IZBA: # %bb.0: 749; RV64IZBA-NEXT: lui a0, 4097 750; RV64IZBA-NEXT: slli a0, a0, 20 751; RV64IZBA-NEXT: ret 752; 753; RV64IZBB-LABEL: imm_left_shifted_lui_3: 754; RV64IZBB: # %bb.0: 755; RV64IZBB-NEXT: lui a0, 4097 756; RV64IZBB-NEXT: slli a0, a0, 20 757; RV64IZBB-NEXT: ret 758; 759; RV64IZBS-LABEL: imm_left_shifted_lui_3: 760; RV64IZBS: # %bb.0: 761; RV64IZBS-NEXT: lui a0, 4097 762; RV64IZBS-NEXT: slli a0, a0, 20 763; RV64IZBS-NEXT: ret 764 ret i64 17596481011712 ; 0x1001_0000_0000 765} 766 767; Various cases where extraneous ADDIs can be inserted where a (right shifted) 768; LUI suffices, or where multiple ADDIs can be used instead of a single LUI. 769 770define i64 @imm_right_shifted_lui_1() nounwind { 771; RV32I-LABEL: imm_right_shifted_lui_1: 772; RV32I: # %bb.0: 773; RV32I-NEXT: lui a0, 1048575 774; RV32I-NEXT: addi a0, a0, 1 775; RV32I-NEXT: lui a1, 16 776; RV32I-NEXT: addi a1, a1, -1 777; RV32I-NEXT: ret 778; 779; RV64I-LABEL: imm_right_shifted_lui_1: 780; RV64I: # %bb.0: 781; RV64I-NEXT: lui a0, 983056 782; RV64I-NEXT: srli a0, a0, 16 783; RV64I-NEXT: ret 784; 785; RV64IZBA-LABEL: imm_right_shifted_lui_1: 786; RV64IZBA: # %bb.0: 787; RV64IZBA-NEXT: lui a0, 983056 788; RV64IZBA-NEXT: srli a0, a0, 16 789; RV64IZBA-NEXT: ret 790; 791; RV64IZBB-LABEL: imm_right_shifted_lui_1: 792; RV64IZBB: # %bb.0: 793; RV64IZBB-NEXT: lui a0, 983056 794; RV64IZBB-NEXT: srli a0, a0, 16 795; RV64IZBB-NEXT: ret 796; 797; RV64IZBS-LABEL: imm_right_shifted_lui_1: 798; RV64IZBS: # %bb.0: 799; RV64IZBS-NEXT: lui a0, 983056 800; RV64IZBS-NEXT: srli a0, a0, 16 801; RV64IZBS-NEXT: ret 802 ret i64 281474976706561 ; 0xFFFF_FFFF_F001 803} 804 805define i64 @imm_right_shifted_lui_2() nounwind { 806; RV32I-LABEL: imm_right_shifted_lui_2: 807; RV32I: # %bb.0: 808; RV32I-NEXT: lui a0, 1048575 809; RV32I-NEXT: addi a0, a0, 1 810; RV32I-NEXT: li a1, 255 811; RV32I-NEXT: ret 812; 813; RV64I-LABEL: imm_right_shifted_lui_2: 814; RV64I: # %bb.0: 815; RV64I-NEXT: lui a0, 1044481 816; RV64I-NEXT: slli a0, a0, 12 817; RV64I-NEXT: srli a0, a0, 24 818; RV64I-NEXT: ret 819; 820; RV64IZBA-LABEL: imm_right_shifted_lui_2: 821; RV64IZBA: # %bb.0: 822; RV64IZBA-NEXT: lui a0, 1044481 823; RV64IZBA-NEXT: slli a0, a0, 12 824; RV64IZBA-NEXT: srli a0, a0, 24 825; RV64IZBA-NEXT: ret 826; 827; RV64IZBB-LABEL: imm_right_shifted_lui_2: 828; RV64IZBB: # %bb.0: 829; RV64IZBB-NEXT: lui a0, 1044481 830; RV64IZBB-NEXT: slli a0, a0, 12 831; RV64IZBB-NEXT: srli a0, a0, 24 832; RV64IZBB-NEXT: ret 833; 834; RV64IZBS-LABEL: imm_right_shifted_lui_2: 835; RV64IZBS: # %bb.0: 836; RV64IZBS-NEXT: lui a0, 1044481 837; RV64IZBS-NEXT: slli a0, a0, 12 838; RV64IZBS-NEXT: srli a0, a0, 24 839; RV64IZBS-NEXT: ret 840 ret i64 1099511623681 ; 0xFF_FFFF_F001 841} 842 843; We can materialize the upper bits with a single (shifted) LUI, but that option 844; can be missed due to the lower bits, which aren't just 1s or just 0s. 845 846define i64 @imm_decoupled_lui_addi() nounwind { 847; RV32I-LABEL: imm_decoupled_lui_addi: 848; RV32I: # %bb.0: 849; RV32I-NEXT: li a0, -3 850; RV32I-NEXT: lui a1, 1 851; RV32I-NEXT: ret 852; 853; RV64I-LABEL: imm_decoupled_lui_addi: 854; RV64I: # %bb.0: 855; RV64I-NEXT: lui a0, 4097 856; RV64I-NEXT: slli a0, a0, 20 857; RV64I-NEXT: addi a0, a0, -3 858; RV64I-NEXT: ret 859; 860; RV64IZBA-LABEL: imm_decoupled_lui_addi: 861; RV64IZBA: # %bb.0: 862; RV64IZBA-NEXT: lui a0, 4097 863; RV64IZBA-NEXT: slli a0, a0, 20 864; RV64IZBA-NEXT: addi a0, a0, -3 865; RV64IZBA-NEXT: ret 866; 867; RV64IZBB-LABEL: imm_decoupled_lui_addi: 868; RV64IZBB: # %bb.0: 869; RV64IZBB-NEXT: lui a0, 4097 870; RV64IZBB-NEXT: slli a0, a0, 20 871; RV64IZBB-NEXT: addi a0, a0, -3 872; RV64IZBB-NEXT: ret 873; 874; RV64IZBS-LABEL: imm_decoupled_lui_addi: 875; RV64IZBS: # %bb.0: 876; RV64IZBS-NEXT: lui a0, 4097 877; RV64IZBS-NEXT: slli a0, a0, 20 878; RV64IZBS-NEXT: addi a0, a0, -3 879; RV64IZBS-NEXT: ret 880 ret i64 17596481011709 ; 0x1000_FFFF_FFFD 881} 882 883; This constant can be materialized for RV64 with LUI+SRLI+XORI. 884 885define i64 @imm_end_xori_1() nounwind { 886; RV32I-LABEL: imm_end_xori_1: 887; RV32I: # %bb.0: 888; RV32I-NEXT: lui a0, 8192 889; RV32I-NEXT: addi a0, a0, -1 890; RV32I-NEXT: lui a1, 917504 891; RV32I-NEXT: ret 892; 893; RV64I-LABEL: imm_end_xori_1: 894; RV64I: # %bb.0: 895; RV64I-NEXT: li a0, -1 896; RV64I-NEXT: slli a0, a0, 36 897; RV64I-NEXT: addi a0, a0, 1 898; RV64I-NEXT: slli a0, a0, 25 899; RV64I-NEXT: addi a0, a0, -1 900; RV64I-NEXT: ret 901; 902; RV64IZBA-LABEL: imm_end_xori_1: 903; RV64IZBA: # %bb.0: 904; RV64IZBA-NEXT: li a0, -1 905; RV64IZBA-NEXT: slli a0, a0, 36 906; RV64IZBA-NEXT: addi a0, a0, 1 907; RV64IZBA-NEXT: slli a0, a0, 25 908; RV64IZBA-NEXT: addi a0, a0, -1 909; RV64IZBA-NEXT: ret 910; 911; RV64IZBB-LABEL: imm_end_xori_1: 912; RV64IZBB: # %bb.0: 913; RV64IZBB-NEXT: li a0, -1 914; RV64IZBB-NEXT: slli a0, a0, 36 915; RV64IZBB-NEXT: addi a0, a0, 1 916; RV64IZBB-NEXT: slli a0, a0, 25 917; RV64IZBB-NEXT: addi a0, a0, -1 918; RV64IZBB-NEXT: ret 919; 920; RV64IZBS-LABEL: imm_end_xori_1: 921; RV64IZBS: # %bb.0: 922; RV64IZBS-NEXT: li a0, -1 923; RV64IZBS-NEXT: slli a0, a0, 36 924; RV64IZBS-NEXT: addi a0, a0, 1 925; RV64IZBS-NEXT: slli a0, a0, 25 926; RV64IZBS-NEXT: addi a0, a0, -1 927; RV64IZBS-NEXT: ret 928 ret i64 -2305843009180139521 ; 0xE000_0000_01FF_FFFF 929} 930 931; This constant can be materialized for RV64 with ADDI+SLLI+ADDI+ADDI. 932 933define i64 @imm_end_2addi_1() nounwind { 934; RV32I-LABEL: imm_end_2addi_1: 935; RV32I: # %bb.0: 936; RV32I-NEXT: lui a0, 1048575 937; RV32I-NEXT: addi a0, a0, 2047 938; RV32I-NEXT: lui a1, 1048512 939; RV32I-NEXT: addi a1, a1, 127 940; RV32I-NEXT: ret 941; 942; RV64I-LABEL: imm_end_2addi_1: 943; RV64I: # %bb.0: 944; RV64I-NEXT: li a0, -2047 945; RV64I-NEXT: slli a0, a0, 27 946; RV64I-NEXT: addi a0, a0, -1 947; RV64I-NEXT: slli a0, a0, 12 948; RV64I-NEXT: addi a0, a0, 2047 949; RV64I-NEXT: ret 950; 951; RV64IZBA-LABEL: imm_end_2addi_1: 952; RV64IZBA: # %bb.0: 953; RV64IZBA-NEXT: li a0, -2047 954; RV64IZBA-NEXT: slli a0, a0, 27 955; RV64IZBA-NEXT: addi a0, a0, -1 956; RV64IZBA-NEXT: slli a0, a0, 12 957; RV64IZBA-NEXT: addi a0, a0, 2047 958; RV64IZBA-NEXT: ret 959; 960; RV64IZBB-LABEL: imm_end_2addi_1: 961; RV64IZBB: # %bb.0: 962; RV64IZBB-NEXT: li a0, -2047 963; RV64IZBB-NEXT: slli a0, a0, 27 964; RV64IZBB-NEXT: addi a0, a0, -1 965; RV64IZBB-NEXT: slli a0, a0, 12 966; RV64IZBB-NEXT: addi a0, a0, 2047 967; RV64IZBB-NEXT: ret 968; 969; RV64IZBS-LABEL: imm_end_2addi_1: 970; RV64IZBS: # %bb.0: 971; RV64IZBS-NEXT: li a0, -2047 972; RV64IZBS-NEXT: slli a0, a0, 27 973; RV64IZBS-NEXT: addi a0, a0, -1 974; RV64IZBS-NEXT: slli a0, a0, 12 975; RV64IZBS-NEXT: addi a0, a0, 2047 976; RV64IZBS-NEXT: ret 977 ret i64 -1125350151030785 ; 0xFFFC_007F_FFFF_F7FF 978} 979 980; This constant can be more efficiently materialized for RV64 if we use two 981; registers instead of one. 982 983define i64 @imm_2reg_1() nounwind { 984; RV32I-LABEL: imm_2reg_1: 985; RV32I: # %bb.0: 986; RV32I-NEXT: lui a0, 74565 987; RV32I-NEXT: addi a0, a0, 1656 988; RV32I-NEXT: lui a1, 983040 989; RV32I-NEXT: ret 990; 991; RV64I-LABEL: imm_2reg_1: 992; RV64I: # %bb.0: 993; RV64I-NEXT: li a0, -1 994; RV64I-NEXT: slli a0, a0, 35 995; RV64I-NEXT: addi a0, a0, 9 996; RV64I-NEXT: slli a0, a0, 13 997; RV64I-NEXT: addi a0, a0, 837 998; RV64I-NEXT: slli a0, a0, 12 999; RV64I-NEXT: addi a0, a0, 1656 1000; RV64I-NEXT: ret 1001; 1002; RV64IZBA-LABEL: imm_2reg_1: 1003; RV64IZBA: # %bb.0: 1004; RV64IZBA-NEXT: li a0, -1 1005; RV64IZBA-NEXT: slli a0, a0, 35 1006; RV64IZBA-NEXT: addi a0, a0, 9 1007; RV64IZBA-NEXT: slli a0, a0, 13 1008; RV64IZBA-NEXT: addi a0, a0, 837 1009; RV64IZBA-NEXT: slli a0, a0, 12 1010; RV64IZBA-NEXT: addi a0, a0, 1656 1011; RV64IZBA-NEXT: ret 1012; 1013; RV64IZBB-LABEL: imm_2reg_1: 1014; RV64IZBB: # %bb.0: 1015; RV64IZBB-NEXT: li a0, -1 1016; RV64IZBB-NEXT: slli a0, a0, 35 1017; RV64IZBB-NEXT: addi a0, a0, 9 1018; RV64IZBB-NEXT: slli a0, a0, 13 1019; RV64IZBB-NEXT: addi a0, a0, 837 1020; RV64IZBB-NEXT: slli a0, a0, 12 1021; RV64IZBB-NEXT: addi a0, a0, 1656 1022; RV64IZBB-NEXT: ret 1023; 1024; RV64IZBS-LABEL: imm_2reg_1: 1025; RV64IZBS: # %bb.0: 1026; RV64IZBS-NEXT: lui a0, 74565 1027; RV64IZBS-NEXT: addiw a0, a0, 1656 1028; RV64IZBS-NEXT: bseti a0, a0, 60 1029; RV64IZBS-NEXT: bseti a0, a0, 61 1030; RV64IZBS-NEXT: bseti a0, a0, 62 1031; RV64IZBS-NEXT: bseti a0, a0, 63 1032; RV64IZBS-NEXT: ret 1033 ret i64 -1152921504301427080 ; 0xF000_0000_1234_5678 1034} 1035 1036; FIXME: This should use a single ADDI for the immediate. 1037define void @imm_store_i16_neg1(i16* %p) nounwind { 1038; RV32I-LABEL: imm_store_i16_neg1: 1039; RV32I: # %bb.0: 1040; RV32I-NEXT: li a1, -1 1041; RV32I-NEXT: sh a1, 0(a0) 1042; RV32I-NEXT: ret 1043; 1044; RV64I-LABEL: imm_store_i16_neg1: 1045; RV64I: # %bb.0: 1046; RV64I-NEXT: li a1, -1 1047; RV64I-NEXT: sh a1, 0(a0) 1048; RV64I-NEXT: ret 1049; 1050; RV64IZBA-LABEL: imm_store_i16_neg1: 1051; RV64IZBA: # %bb.0: 1052; RV64IZBA-NEXT: li a1, -1 1053; RV64IZBA-NEXT: sh a1, 0(a0) 1054; RV64IZBA-NEXT: ret 1055; 1056; RV64IZBB-LABEL: imm_store_i16_neg1: 1057; RV64IZBB: # %bb.0: 1058; RV64IZBB-NEXT: li a1, -1 1059; RV64IZBB-NEXT: sh a1, 0(a0) 1060; RV64IZBB-NEXT: ret 1061; 1062; RV64IZBS-LABEL: imm_store_i16_neg1: 1063; RV64IZBS: # %bb.0: 1064; RV64IZBS-NEXT: li a1, -1 1065; RV64IZBS-NEXT: sh a1, 0(a0) 1066; RV64IZBS-NEXT: ret 1067 store i16 -1, i16* %p 1068 ret void 1069} 1070 1071; FIXME: This should use a single ADDI for the immediate. 1072define void @imm_store_i32_neg1(i32* %p) nounwind { 1073; RV32I-LABEL: imm_store_i32_neg1: 1074; RV32I: # %bb.0: 1075; RV32I-NEXT: li a1, -1 1076; RV32I-NEXT: sw a1, 0(a0) 1077; RV32I-NEXT: ret 1078; 1079; RV64I-LABEL: imm_store_i32_neg1: 1080; RV64I: # %bb.0: 1081; RV64I-NEXT: li a1, -1 1082; RV64I-NEXT: sw a1, 0(a0) 1083; RV64I-NEXT: ret 1084; 1085; RV64IZBA-LABEL: imm_store_i32_neg1: 1086; RV64IZBA: # %bb.0: 1087; RV64IZBA-NEXT: li a1, -1 1088; RV64IZBA-NEXT: sw a1, 0(a0) 1089; RV64IZBA-NEXT: ret 1090; 1091; RV64IZBB-LABEL: imm_store_i32_neg1: 1092; RV64IZBB: # %bb.0: 1093; RV64IZBB-NEXT: li a1, -1 1094; RV64IZBB-NEXT: sw a1, 0(a0) 1095; RV64IZBB-NEXT: ret 1096; 1097; RV64IZBS-LABEL: imm_store_i32_neg1: 1098; RV64IZBS: # %bb.0: 1099; RV64IZBS-NEXT: li a1, -1 1100; RV64IZBS-NEXT: sw a1, 0(a0) 1101; RV64IZBS-NEXT: ret 1102 store i32 -1, i32* %p 1103 ret void 1104} 1105 1106define i64 @imm_5372288229() { 1107; RV32I-LABEL: imm_5372288229: 1108; RV32I: # %bb.0: 1109; RV32I-NEXT: lui a0, 263018 1110; RV32I-NEXT: addi a0, a0, -795 1111; RV32I-NEXT: li a1, 1 1112; RV32I-NEXT: ret 1113; 1114; RV64I-LABEL: imm_5372288229: 1115; RV64I: # %bb.0: 1116; RV64I-NEXT: lui a0, 160 1117; RV64I-NEXT: addiw a0, a0, 437 1118; RV64I-NEXT: slli a0, a0, 13 1119; RV64I-NEXT: addi a0, a0, -795 1120; RV64I-NEXT: ret 1121; 1122; RV64IZBA-LABEL: imm_5372288229: 1123; RV64IZBA: # %bb.0: 1124; RV64IZBA-NEXT: lui a0, 655797 1125; RV64IZBA-NEXT: slli.uw a0, a0, 1 1126; RV64IZBA-NEXT: addi a0, a0, -795 1127; RV64IZBA-NEXT: ret 1128; 1129; RV64IZBB-LABEL: imm_5372288229: 1130; RV64IZBB: # %bb.0: 1131; RV64IZBB-NEXT: lui a0, 160 1132; RV64IZBB-NEXT: addiw a0, a0, 437 1133; RV64IZBB-NEXT: slli a0, a0, 13 1134; RV64IZBB-NEXT: addi a0, a0, -795 1135; RV64IZBB-NEXT: ret 1136; 1137; RV64IZBS-LABEL: imm_5372288229: 1138; RV64IZBS: # %bb.0: 1139; RV64IZBS-NEXT: lui a0, 263018 1140; RV64IZBS-NEXT: addiw a0, a0, -795 1141; RV64IZBS-NEXT: bseti a0, a0, 32 1142; RV64IZBS-NEXT: ret 1143 ret i64 5372288229 1144} 1145 1146define i64 @imm_neg_5372288229() { 1147; RV32I-LABEL: imm_neg_5372288229: 1148; RV32I: # %bb.0: 1149; RV32I-NEXT: lui a0, 785558 1150; RV32I-NEXT: addi a0, a0, 795 1151; RV32I-NEXT: li a1, -2 1152; RV32I-NEXT: ret 1153; 1154; RV64I-LABEL: imm_neg_5372288229: 1155; RV64I: # %bb.0: 1156; RV64I-NEXT: lui a0, 1048416 1157; RV64I-NEXT: addiw a0, a0, -437 1158; RV64I-NEXT: slli a0, a0, 13 1159; RV64I-NEXT: addi a0, a0, 795 1160; RV64I-NEXT: ret 1161; 1162; RV64IZBA-LABEL: imm_neg_5372288229: 1163; RV64IZBA: # %bb.0: 1164; RV64IZBA-NEXT: lui a0, 611378 1165; RV64IZBA-NEXT: addiw a0, a0, 265 1166; RV64IZBA-NEXT: sh1add a0, a0, a0 1167; RV64IZBA-NEXT: ret 1168; 1169; RV64IZBB-LABEL: imm_neg_5372288229: 1170; RV64IZBB: # %bb.0: 1171; RV64IZBB-NEXT: lui a0, 1048416 1172; RV64IZBB-NEXT: addiw a0, a0, -437 1173; RV64IZBB-NEXT: slli a0, a0, 13 1174; RV64IZBB-NEXT: addi a0, a0, 795 1175; RV64IZBB-NEXT: ret 1176; 1177; RV64IZBS-LABEL: imm_neg_5372288229: 1178; RV64IZBS: # %bb.0: 1179; RV64IZBS-NEXT: lui a0, 785558 1180; RV64IZBS-NEXT: addiw a0, a0, 795 1181; RV64IZBS-NEXT: bclri a0, a0, 32 1182; RV64IZBS-NEXT: ret 1183 ret i64 -5372288229 1184} 1185 1186define i64 @imm_8953813715() { 1187; RV32I-LABEL: imm_8953813715: 1188; RV32I: # %bb.0: 1189; RV32I-NEXT: lui a0, 88838 1190; RV32I-NEXT: addi a0, a0, -1325 1191; RV32I-NEXT: li a1, 2 1192; RV32I-NEXT: ret 1193; 1194; RV64I-LABEL: imm_8953813715: 1195; RV64I: # %bb.0: 1196; RV64I-NEXT: lui a0, 267 1197; RV64I-NEXT: addiw a0, a0, -637 1198; RV64I-NEXT: slli a0, a0, 13 1199; RV64I-NEXT: addi a0, a0, -1325 1200; RV64I-NEXT: ret 1201; 1202; RV64IZBA-LABEL: imm_8953813715: 1203; RV64IZBA: # %bb.0: 1204; RV64IZBA-NEXT: lui a0, 437198 1205; RV64IZBA-NEXT: addiw a0, a0, -265 1206; RV64IZBA-NEXT: sh2add a0, a0, a0 1207; RV64IZBA-NEXT: ret 1208; 1209; RV64IZBB-LABEL: imm_8953813715: 1210; RV64IZBB: # %bb.0: 1211; RV64IZBB-NEXT: lui a0, 267 1212; RV64IZBB-NEXT: addiw a0, a0, -637 1213; RV64IZBB-NEXT: slli a0, a0, 13 1214; RV64IZBB-NEXT: addi a0, a0, -1325 1215; RV64IZBB-NEXT: ret 1216; 1217; RV64IZBS-LABEL: imm_8953813715: 1218; RV64IZBS: # %bb.0: 1219; RV64IZBS-NEXT: lui a0, 88838 1220; RV64IZBS-NEXT: addiw a0, a0, -1325 1221; RV64IZBS-NEXT: bseti a0, a0, 33 1222; RV64IZBS-NEXT: ret 1223 ret i64 8953813715 1224} 1225 1226define i64 @imm_neg_8953813715() { 1227; RV32I-LABEL: imm_neg_8953813715: 1228; RV32I: # %bb.0: 1229; RV32I-NEXT: lui a0, 959738 1230; RV32I-NEXT: addi a0, a0, 1325 1231; RV32I-NEXT: li a1, -3 1232; RV32I-NEXT: ret 1233; 1234; RV64I-LABEL: imm_neg_8953813715: 1235; RV64I: # %bb.0: 1236; RV64I-NEXT: lui a0, 1048309 1237; RV64I-NEXT: addiw a0, a0, 637 1238; RV64I-NEXT: slli a0, a0, 13 1239; RV64I-NEXT: addi a0, a0, 1325 1240; RV64I-NEXT: ret 1241; 1242; RV64IZBA-LABEL: imm_neg_8953813715: 1243; RV64IZBA: # %bb.0: 1244; RV64IZBA-NEXT: lui a0, 611378 1245; RV64IZBA-NEXT: addiw a0, a0, 265 1246; RV64IZBA-NEXT: sh2add a0, a0, a0 1247; RV64IZBA-NEXT: ret 1248; 1249; RV64IZBB-LABEL: imm_neg_8953813715: 1250; RV64IZBB: # %bb.0: 1251; RV64IZBB-NEXT: lui a0, 1048309 1252; RV64IZBB-NEXT: addiw a0, a0, 637 1253; RV64IZBB-NEXT: slli a0, a0, 13 1254; RV64IZBB-NEXT: addi a0, a0, 1325 1255; RV64IZBB-NEXT: ret 1256; 1257; RV64IZBS-LABEL: imm_neg_8953813715: 1258; RV64IZBS: # %bb.0: 1259; RV64IZBS-NEXT: lui a0, 959738 1260; RV64IZBS-NEXT: addiw a0, a0, 1325 1261; RV64IZBS-NEXT: bclri a0, a0, 33 1262; RV64IZBS-NEXT: ret 1263 ret i64 -8953813715 1264} 1265 1266define i64 @imm_16116864687() { 1267; RV32I-LABEL: imm_16116864687: 1268; RV32I: # %bb.0: 1269; RV32I-NEXT: lui a0, 789053 1270; RV32I-NEXT: addi a0, a0, 1711 1271; RV32I-NEXT: li a1, 3 1272; RV32I-NEXT: ret 1273; 1274; RV64I-LABEL: imm_16116864687: 1275; RV64I: # %bb.0: 1276; RV64I-NEXT: lui a0, 961 1277; RV64I-NEXT: addiw a0, a0, -1475 1278; RV64I-NEXT: slli a0, a0, 12 1279; RV64I-NEXT: addi a0, a0, 1711 1280; RV64I-NEXT: ret 1281; 1282; RV64IZBA-LABEL: imm_16116864687: 1283; RV64IZBA: # %bb.0: 1284; RV64IZBA-NEXT: lui a0, 437198 1285; RV64IZBA-NEXT: addiw a0, a0, -265 1286; RV64IZBA-NEXT: sh3add a0, a0, a0 1287; RV64IZBA-NEXT: ret 1288; 1289; RV64IZBB-LABEL: imm_16116864687: 1290; RV64IZBB: # %bb.0: 1291; RV64IZBB-NEXT: lui a0, 961 1292; RV64IZBB-NEXT: addiw a0, a0, -1475 1293; RV64IZBB-NEXT: slli a0, a0, 12 1294; RV64IZBB-NEXT: addi a0, a0, 1711 1295; RV64IZBB-NEXT: ret 1296; 1297; RV64IZBS-LABEL: imm_16116864687: 1298; RV64IZBS: # %bb.0: 1299; RV64IZBS-NEXT: lui a0, 961 1300; RV64IZBS-NEXT: addiw a0, a0, -1475 1301; RV64IZBS-NEXT: slli a0, a0, 12 1302; RV64IZBS-NEXT: addi a0, a0, 1711 1303; RV64IZBS-NEXT: ret 1304 ret i64 16116864687 1305} 1306 1307define i64 @imm_neg_16116864687() { 1308; RV32I-LABEL: imm_neg_16116864687: 1309; RV32I: # %bb.0: 1310; RV32I-NEXT: lui a0, 259523 1311; RV32I-NEXT: addi a0, a0, -1711 1312; RV32I-NEXT: li a1, -4 1313; RV32I-NEXT: ret 1314; 1315; RV64I-LABEL: imm_neg_16116864687: 1316; RV64I: # %bb.0: 1317; RV64I-NEXT: lui a0, 1047615 1318; RV64I-NEXT: addiw a0, a0, 1475 1319; RV64I-NEXT: slli a0, a0, 12 1320; RV64I-NEXT: addi a0, a0, -1711 1321; RV64I-NEXT: ret 1322; 1323; RV64IZBA-LABEL: imm_neg_16116864687: 1324; RV64IZBA: # %bb.0: 1325; RV64IZBA-NEXT: lui a0, 611378 1326; RV64IZBA-NEXT: addiw a0, a0, 265 1327; RV64IZBA-NEXT: sh3add a0, a0, a0 1328; RV64IZBA-NEXT: ret 1329; 1330; RV64IZBB-LABEL: imm_neg_16116864687: 1331; RV64IZBB: # %bb.0: 1332; RV64IZBB-NEXT: lui a0, 1047615 1333; RV64IZBB-NEXT: addiw a0, a0, 1475 1334; RV64IZBB-NEXT: slli a0, a0, 12 1335; RV64IZBB-NEXT: addi a0, a0, -1711 1336; RV64IZBB-NEXT: ret 1337; 1338; RV64IZBS-LABEL: imm_neg_16116864687: 1339; RV64IZBS: # %bb.0: 1340; RV64IZBS-NEXT: lui a0, 1047615 1341; RV64IZBS-NEXT: addiw a0, a0, 1475 1342; RV64IZBS-NEXT: slli a0, a0, 12 1343; RV64IZBS-NEXT: addi a0, a0, -1711 1344; RV64IZBS-NEXT: ret 1345 ret i64 -16116864687 1346} 1347 1348define i64 @imm_2344336315() { 1349; RV32I-LABEL: imm_2344336315: 1350; RV32I: # %bb.0: 1351; RV32I-NEXT: lui a0, 572348 1352; RV32I-NEXT: addi a0, a0, -1093 1353; RV32I-NEXT: li a1, 0 1354; RV32I-NEXT: ret 1355; 1356; RV64I-LABEL: imm_2344336315: 1357; RV64I: # %bb.0: 1358; RV64I-NEXT: lui a0, 143087 1359; RV64I-NEXT: slli a0, a0, 2 1360; RV64I-NEXT: addi a0, a0, -1093 1361; RV64I-NEXT: ret 1362; 1363; RV64IZBA-LABEL: imm_2344336315: 1364; RV64IZBA: # %bb.0: 1365; RV64IZBA-NEXT: lui a0, 143087 1366; RV64IZBA-NEXT: slli a0, a0, 2 1367; RV64IZBA-NEXT: addi a0, a0, -1093 1368; RV64IZBA-NEXT: ret 1369; 1370; RV64IZBB-LABEL: imm_2344336315: 1371; RV64IZBB: # %bb.0: 1372; RV64IZBB-NEXT: lui a0, 143087 1373; RV64IZBB-NEXT: slli a0, a0, 2 1374; RV64IZBB-NEXT: addi a0, a0, -1093 1375; RV64IZBB-NEXT: ret 1376; 1377; RV64IZBS-LABEL: imm_2344336315: 1378; RV64IZBS: # %bb.0: 1379; RV64IZBS-NEXT: lui a0, 143087 1380; RV64IZBS-NEXT: slli a0, a0, 2 1381; RV64IZBS-NEXT: addi a0, a0, -1093 1382; RV64IZBS-NEXT: ret 1383 ret i64 2344336315 ; 0x8bbbbbbb 1384} 1385 1386define i64 @imm_70370820078523() { 1387; RV32I-LABEL: imm_70370820078523: 1388; RV32I: # %bb.0: 1389; RV32I-NEXT: lui a0, 506812 1390; RV32I-NEXT: addi a0, a0, -1093 1391; RV32I-NEXT: lui a1, 4 1392; RV32I-NEXT: ret 1393; 1394; RV64I-LABEL: imm_70370820078523: 1395; RV64I: # %bb.0: 1396; RV64I-NEXT: lui a0, 256 1397; RV64I-NEXT: addiw a0, a0, 31 1398; RV64I-NEXT: slli a0, a0, 12 1399; RV64I-NEXT: addi a0, a0, -273 1400; RV64I-NEXT: slli a0, a0, 14 1401; RV64I-NEXT: addi a0, a0, -1093 1402; RV64I-NEXT: ret 1403; 1404; RV64IZBA-LABEL: imm_70370820078523: 1405; RV64IZBA: # %bb.0: 1406; RV64IZBA-NEXT: lui a0, 256 1407; RV64IZBA-NEXT: addiw a0, a0, 31 1408; RV64IZBA-NEXT: slli a0, a0, 12 1409; RV64IZBA-NEXT: addi a0, a0, -273 1410; RV64IZBA-NEXT: slli a0, a0, 14 1411; RV64IZBA-NEXT: addi a0, a0, -1093 1412; RV64IZBA-NEXT: ret 1413; 1414; RV64IZBB-LABEL: imm_70370820078523: 1415; RV64IZBB: # %bb.0: 1416; RV64IZBB-NEXT: lui a0, 256 1417; RV64IZBB-NEXT: addiw a0, a0, 31 1418; RV64IZBB-NEXT: slli a0, a0, 12 1419; RV64IZBB-NEXT: addi a0, a0, -273 1420; RV64IZBB-NEXT: slli a0, a0, 14 1421; RV64IZBB-NEXT: addi a0, a0, -1093 1422; RV64IZBB-NEXT: ret 1423; 1424; RV64IZBS-LABEL: imm_70370820078523: 1425; RV64IZBS: # %bb.0: 1426; RV64IZBS-NEXT: lui a0, 506812 1427; RV64IZBS-NEXT: addiw a0, a0, -1093 1428; RV64IZBS-NEXT: bseti a0, a0, 46 1429; RV64IZBS-NEXT: ret 1430 ret i64 70370820078523 ; 0x40007bbbbbbb 1431} 1432 1433define i64 @imm_neg_9223372034778874949() { 1434; RV32I-LABEL: imm_neg_9223372034778874949: 1435; RV32I: # %bb.0: 1436; RV32I-NEXT: lui a0, 506812 1437; RV32I-NEXT: addi a0, a0, -1093 1438; RV32I-NEXT: lui a1, 524288 1439; RV32I-NEXT: ret 1440; 1441; RV64I-LABEL: imm_neg_9223372034778874949: 1442; RV64I: # %bb.0: 1443; RV64I-NEXT: li a0, -1 1444; RV64I-NEXT: slli a0, a0, 37 1445; RV64I-NEXT: addi a0, a0, 31 1446; RV64I-NEXT: slli a0, a0, 12 1447; RV64I-NEXT: addi a0, a0, -273 1448; RV64I-NEXT: slli a0, a0, 14 1449; RV64I-NEXT: addi a0, a0, -1093 1450; RV64I-NEXT: ret 1451; 1452; RV64IZBA-LABEL: imm_neg_9223372034778874949: 1453; RV64IZBA: # %bb.0: 1454; RV64IZBA-NEXT: li a0, -1 1455; RV64IZBA-NEXT: slli a0, a0, 37 1456; RV64IZBA-NEXT: addi a0, a0, 31 1457; RV64IZBA-NEXT: slli a0, a0, 12 1458; RV64IZBA-NEXT: addi a0, a0, -273 1459; RV64IZBA-NEXT: slli a0, a0, 14 1460; RV64IZBA-NEXT: addi a0, a0, -1093 1461; RV64IZBA-NEXT: ret 1462; 1463; RV64IZBB-LABEL: imm_neg_9223372034778874949: 1464; RV64IZBB: # %bb.0: 1465; RV64IZBB-NEXT: li a0, -1 1466; RV64IZBB-NEXT: slli a0, a0, 37 1467; RV64IZBB-NEXT: addi a0, a0, 31 1468; RV64IZBB-NEXT: slli a0, a0, 12 1469; RV64IZBB-NEXT: addi a0, a0, -273 1470; RV64IZBB-NEXT: slli a0, a0, 14 1471; RV64IZBB-NEXT: addi a0, a0, -1093 1472; RV64IZBB-NEXT: ret 1473; 1474; RV64IZBS-LABEL: imm_neg_9223372034778874949: 1475; RV64IZBS: # %bb.0: 1476; RV64IZBS-NEXT: lui a0, 506812 1477; RV64IZBS-NEXT: addiw a0, a0, -1093 1478; RV64IZBS-NEXT: bseti a0, a0, 63 1479; RV64IZBS-NEXT: ret 1480 ret i64 -9223372034778874949 ; 0x800000007bbbbbbb 1481} 1482 1483define i64 @imm_neg_9223301666034697285() { 1484; RV32I-LABEL: imm_neg_9223301666034697285: 1485; RV32I: # %bb.0: 1486; RV32I-NEXT: lui a0, 506812 1487; RV32I-NEXT: addi a0, a0, -1093 1488; RV32I-NEXT: lui a1, 524292 1489; RV32I-NEXT: ret 1490; 1491; RV64I-LABEL: imm_neg_9223301666034697285: 1492; RV64I: # %bb.0: 1493; RV64I-NEXT: lui a0, 917505 1494; RV64I-NEXT: slli a0, a0, 8 1495; RV64I-NEXT: addi a0, a0, 31 1496; RV64I-NEXT: slli a0, a0, 12 1497; RV64I-NEXT: addi a0, a0, -273 1498; RV64I-NEXT: slli a0, a0, 14 1499; RV64I-NEXT: addi a0, a0, -1093 1500; RV64I-NEXT: ret 1501; 1502; RV64IZBA-LABEL: imm_neg_9223301666034697285: 1503; RV64IZBA: # %bb.0: 1504; RV64IZBA-NEXT: lui a0, 917505 1505; RV64IZBA-NEXT: slli a0, a0, 8 1506; RV64IZBA-NEXT: addi a0, a0, 31 1507; RV64IZBA-NEXT: slli a0, a0, 12 1508; RV64IZBA-NEXT: addi a0, a0, -273 1509; RV64IZBA-NEXT: slli a0, a0, 14 1510; RV64IZBA-NEXT: addi a0, a0, -1093 1511; RV64IZBA-NEXT: ret 1512; 1513; RV64IZBB-LABEL: imm_neg_9223301666034697285: 1514; RV64IZBB: # %bb.0: 1515; RV64IZBB-NEXT: lui a0, 917505 1516; RV64IZBB-NEXT: slli a0, a0, 8 1517; RV64IZBB-NEXT: addi a0, a0, 31 1518; RV64IZBB-NEXT: slli a0, a0, 12 1519; RV64IZBB-NEXT: addi a0, a0, -273 1520; RV64IZBB-NEXT: slli a0, a0, 14 1521; RV64IZBB-NEXT: addi a0, a0, -1093 1522; RV64IZBB-NEXT: ret 1523; 1524; RV64IZBS-LABEL: imm_neg_9223301666034697285: 1525; RV64IZBS: # %bb.0: 1526; RV64IZBS-NEXT: lui a0, 506812 1527; RV64IZBS-NEXT: addiw a0, a0, -1093 1528; RV64IZBS-NEXT: bseti a0, a0, 46 1529; RV64IZBS-NEXT: bseti a0, a0, 63 1530; RV64IZBS-NEXT: ret 1531 ret i64 -9223301666034697285 ; 0x800040007bbbbbbb 1532} 1533 1534define i64 @imm_neg_2219066437() { 1535; RV32I-LABEL: imm_neg_2219066437: 1536; RV32I: # %bb.0: 1537; RV32I-NEXT: lui a0, 506812 1538; RV32I-NEXT: addi a0, a0, -1093 1539; RV32I-NEXT: li a1, -1 1540; RV32I-NEXT: ret 1541; 1542; RV64I-LABEL: imm_neg_2219066437: 1543; RV64I: # %bb.0: 1544; RV64I-NEXT: lui a0, 913135 1545; RV64I-NEXT: slli a0, a0, 2 1546; RV64I-NEXT: addi a0, a0, -1093 1547; RV64I-NEXT: ret 1548; 1549; RV64IZBA-LABEL: imm_neg_2219066437: 1550; RV64IZBA: # %bb.0: 1551; RV64IZBA-NEXT: lui a0, 913135 1552; RV64IZBA-NEXT: slli a0, a0, 2 1553; RV64IZBA-NEXT: addi a0, a0, -1093 1554; RV64IZBA-NEXT: ret 1555; 1556; RV64IZBB-LABEL: imm_neg_2219066437: 1557; RV64IZBB: # %bb.0: 1558; RV64IZBB-NEXT: lui a0, 913135 1559; RV64IZBB-NEXT: slli a0, a0, 2 1560; RV64IZBB-NEXT: addi a0, a0, -1093 1561; RV64IZBB-NEXT: ret 1562; 1563; RV64IZBS-LABEL: imm_neg_2219066437: 1564; RV64IZBS: # %bb.0: 1565; RV64IZBS-NEXT: lui a0, 913135 1566; RV64IZBS-NEXT: slli a0, a0, 2 1567; RV64IZBS-NEXT: addi a0, a0, -1093 1568; RV64IZBS-NEXT: ret 1569 ret i64 -2219066437 ; 0xffffffff7bbbbbbb 1570} 1571 1572define i64 @imm_neg_8798043653189() { 1573; RV32I-LABEL: imm_neg_8798043653189: 1574; RV32I: # %bb.0: 1575; RV32I-NEXT: lui a0, 572348 1576; RV32I-NEXT: addi a0, a0, -1093 1577; RV32I-NEXT: lui a1, 1048575 1578; RV32I-NEXT: addi a1, a1, 2047 1579; RV32I-NEXT: ret 1580; 1581; RV64I-LABEL: imm_neg_8798043653189: 1582; RV64I: # %bb.0: 1583; RV64I-NEXT: lui a0, 917475 1584; RV64I-NEXT: addiw a0, a0, -273 1585; RV64I-NEXT: slli a0, a0, 14 1586; RV64I-NEXT: addi a0, a0, -1093 1587; RV64I-NEXT: ret 1588; 1589; RV64IZBA-LABEL: imm_neg_8798043653189: 1590; RV64IZBA: # %bb.0: 1591; RV64IZBA-NEXT: lui a0, 917475 1592; RV64IZBA-NEXT: addiw a0, a0, -273 1593; RV64IZBA-NEXT: slli a0, a0, 14 1594; RV64IZBA-NEXT: addi a0, a0, -1093 1595; RV64IZBA-NEXT: ret 1596; 1597; RV64IZBB-LABEL: imm_neg_8798043653189: 1598; RV64IZBB: # %bb.0: 1599; RV64IZBB-NEXT: lui a0, 917475 1600; RV64IZBB-NEXT: addiw a0, a0, -273 1601; RV64IZBB-NEXT: slli a0, a0, 14 1602; RV64IZBB-NEXT: addi a0, a0, -1093 1603; RV64IZBB-NEXT: ret 1604; 1605; RV64IZBS-LABEL: imm_neg_8798043653189: 1606; RV64IZBS: # %bb.0: 1607; RV64IZBS-NEXT: lui a0, 572348 1608; RV64IZBS-NEXT: addiw a0, a0, -1093 1609; RV64IZBS-NEXT: bclri a0, a0, 43 1610; RV64IZBS-NEXT: ret 1611 ret i64 -8798043653189 ; 0xfffff7ff8bbbbbbb 1612} 1613 1614define i64 @imm_9223372034904144827() { 1615; RV32I-LABEL: imm_9223372034904144827: 1616; RV32I: # %bb.0: 1617; RV32I-NEXT: lui a0, 572348 1618; RV32I-NEXT: addi a0, a0, -1093 1619; RV32I-NEXT: lui a1, 524288 1620; RV32I-NEXT: addi a1, a1, -1 1621; RV32I-NEXT: ret 1622; 1623; RV64I-LABEL: imm_9223372034904144827: 1624; RV64I: # %bb.0: 1625; RV64I-NEXT: lui a0, 1048343 1626; RV64I-NEXT: addiw a0, a0, 1911 1627; RV64I-NEXT: slli a0, a0, 12 1628; RV64I-NEXT: addi a0, a0, 1911 1629; RV64I-NEXT: srli a0, a0, 1 1630; RV64I-NEXT: ret 1631; 1632; RV64IZBA-LABEL: imm_9223372034904144827: 1633; RV64IZBA: # %bb.0: 1634; RV64IZBA-NEXT: lui a0, 1048343 1635; RV64IZBA-NEXT: addiw a0, a0, 1911 1636; RV64IZBA-NEXT: slli a0, a0, 12 1637; RV64IZBA-NEXT: addi a0, a0, 1911 1638; RV64IZBA-NEXT: srli a0, a0, 1 1639; RV64IZBA-NEXT: ret 1640; 1641; RV64IZBB-LABEL: imm_9223372034904144827: 1642; RV64IZBB: # %bb.0: 1643; RV64IZBB-NEXT: lui a0, 1048343 1644; RV64IZBB-NEXT: addiw a0, a0, 1911 1645; RV64IZBB-NEXT: slli a0, a0, 12 1646; RV64IZBB-NEXT: addi a0, a0, 1911 1647; RV64IZBB-NEXT: srli a0, a0, 1 1648; RV64IZBB-NEXT: ret 1649; 1650; RV64IZBS-LABEL: imm_9223372034904144827: 1651; RV64IZBS: # %bb.0: 1652; RV64IZBS-NEXT: lui a0, 572348 1653; RV64IZBS-NEXT: addiw a0, a0, -1093 1654; RV64IZBS-NEXT: bclri a0, a0, 63 1655; RV64IZBS-NEXT: ret 1656 ret i64 9223372034904144827 ; 0x7fffffff8bbbbbbb 1657} 1658 1659define i64 @imm_neg_9223354442718100411() { 1660; RV32I-LABEL: imm_neg_9223354442718100411: 1661; RV32I: # %bb.0: 1662; RV32I-NEXT: lui a0, 572348 1663; RV32I-NEXT: addi a0, a0, -1093 1664; RV32I-NEXT: lui a1, 524287 1665; RV32I-NEXT: addi a1, a1, -1 1666; RV32I-NEXT: ret 1667; 1668; RV64I-LABEL: imm_neg_9223354442718100411: 1669; RV64I: # %bb.0: 1670; RV64I-NEXT: lui a0, 524287 1671; RV64I-NEXT: slli a0, a0, 6 1672; RV64I-NEXT: addi a0, a0, -29 1673; RV64I-NEXT: slli a0, a0, 12 1674; RV64I-NEXT: addi a0, a0, -273 1675; RV64I-NEXT: slli a0, a0, 14 1676; RV64I-NEXT: addi a0, a0, -1093 1677; RV64I-NEXT: ret 1678; 1679; RV64IZBA-LABEL: imm_neg_9223354442718100411: 1680; RV64IZBA: # %bb.0: 1681; RV64IZBA-NEXT: lui a0, 524287 1682; RV64IZBA-NEXT: slli a0, a0, 6 1683; RV64IZBA-NEXT: addi a0, a0, -29 1684; RV64IZBA-NEXT: slli a0, a0, 12 1685; RV64IZBA-NEXT: addi a0, a0, -273 1686; RV64IZBA-NEXT: slli a0, a0, 14 1687; RV64IZBA-NEXT: addi a0, a0, -1093 1688; RV64IZBA-NEXT: ret 1689; 1690; RV64IZBB-LABEL: imm_neg_9223354442718100411: 1691; RV64IZBB: # %bb.0: 1692; RV64IZBB-NEXT: lui a0, 524287 1693; RV64IZBB-NEXT: slli a0, a0, 6 1694; RV64IZBB-NEXT: addi a0, a0, -29 1695; RV64IZBB-NEXT: slli a0, a0, 12 1696; RV64IZBB-NEXT: addi a0, a0, -273 1697; RV64IZBB-NEXT: slli a0, a0, 14 1698; RV64IZBB-NEXT: addi a0, a0, -1093 1699; RV64IZBB-NEXT: ret 1700; 1701; RV64IZBS-LABEL: imm_neg_9223354442718100411: 1702; RV64IZBS: # %bb.0: 1703; RV64IZBS-NEXT: lui a0, 572348 1704; RV64IZBS-NEXT: addiw a0, a0, -1093 1705; RV64IZBS-NEXT: bclri a0, a0, 44 1706; RV64IZBS-NEXT: bclri a0, a0, 63 1707; RV64IZBS-NEXT: ret 1708 ret i64 9223354442718100411 ; 0x7fffefff8bbbbbbb 1709} 1710 1711define i64 @imm_2863311530() { 1712; RV32I-LABEL: imm_2863311530: 1713; RV32I: # %bb.0: 1714; RV32I-NEXT: lui a0, 699051 1715; RV32I-NEXT: addi a0, a0, -1366 1716; RV32I-NEXT: li a1, 0 1717; RV32I-NEXT: ret 1718; 1719; RV64I-LABEL: imm_2863311530: 1720; RV64I: # %bb.0: 1721; RV64I-NEXT: lui a0, 349525 1722; RV64I-NEXT: addiw a0, a0, 1365 1723; RV64I-NEXT: slli a0, a0, 1 1724; RV64I-NEXT: ret 1725; 1726; RV64IZBA-LABEL: imm_2863311530: 1727; RV64IZBA: # %bb.0: 1728; RV64IZBA-NEXT: lui a0, 349525 1729; RV64IZBA-NEXT: addiw a0, a0, 1365 1730; RV64IZBA-NEXT: slli a0, a0, 1 1731; RV64IZBA-NEXT: ret 1732; 1733; RV64IZBB-LABEL: imm_2863311530: 1734; RV64IZBB: # %bb.0: 1735; RV64IZBB-NEXT: lui a0, 349525 1736; RV64IZBB-NEXT: addiw a0, a0, 1365 1737; RV64IZBB-NEXT: slli a0, a0, 1 1738; RV64IZBB-NEXT: ret 1739; 1740; RV64IZBS-LABEL: imm_2863311530: 1741; RV64IZBS: # %bb.0: 1742; RV64IZBS-NEXT: lui a0, 349525 1743; RV64IZBS-NEXT: addiw a0, a0, 1365 1744; RV64IZBS-NEXT: slli a0, a0, 1 1745; RV64IZBS-NEXT: ret 1746 ret i64 2863311530 ; #0xaaaaaaaa 1747} 1748 1749define i64 @imm_neg_2863311530() { 1750; RV32I-LABEL: imm_neg_2863311530: 1751; RV32I: # %bb.0: 1752; RV32I-NEXT: lui a0, 349525 1753; RV32I-NEXT: addi a0, a0, 1366 1754; RV32I-NEXT: li a1, -1 1755; RV32I-NEXT: ret 1756; 1757; RV64I-LABEL: imm_neg_2863311530: 1758; RV64I: # %bb.0: 1759; RV64I-NEXT: lui a0, 699051 1760; RV64I-NEXT: addiw a0, a0, -1365 1761; RV64I-NEXT: slli a0, a0, 1 1762; RV64I-NEXT: ret 1763; 1764; RV64IZBA-LABEL: imm_neg_2863311530: 1765; RV64IZBA: # %bb.0: 1766; RV64IZBA-NEXT: lui a0, 699051 1767; RV64IZBA-NEXT: addiw a0, a0, -1365 1768; RV64IZBA-NEXT: slli a0, a0, 1 1769; RV64IZBA-NEXT: ret 1770; 1771; RV64IZBB-LABEL: imm_neg_2863311530: 1772; RV64IZBB: # %bb.0: 1773; RV64IZBB-NEXT: lui a0, 699051 1774; RV64IZBB-NEXT: addiw a0, a0, -1365 1775; RV64IZBB-NEXT: slli a0, a0, 1 1776; RV64IZBB-NEXT: ret 1777; 1778; RV64IZBS-LABEL: imm_neg_2863311530: 1779; RV64IZBS: # %bb.0: 1780; RV64IZBS-NEXT: lui a0, 699051 1781; RV64IZBS-NEXT: addiw a0, a0, -1365 1782; RV64IZBS-NEXT: slli a0, a0, 1 1783; RV64IZBS-NEXT: ret 1784 ret i64 -2863311530 ; #0xffffffff55555556 1785} 1786 1787define i64 @imm_2147486378() { 1788; RV32I-LABEL: imm_2147486378: 1789; RV32I: # %bb.0: 1790; RV32I-NEXT: lui a0, 524288 1791; RV32I-NEXT: addi a0, a0, 1365 1792; RV32I-NEXT: li a1, 0 1793; RV32I-NEXT: ret 1794; 1795; RV64I-LABEL: imm_2147486378: 1796; RV64I: # %bb.0: 1797; RV64I-NEXT: li a0, 1 1798; RV64I-NEXT: slli a0, a0, 31 1799; RV64I-NEXT: addi a0, a0, 1365 1800; RV64I-NEXT: ret 1801; 1802; RV64IZBA-LABEL: imm_2147486378: 1803; RV64IZBA: # %bb.0: 1804; RV64IZBA-NEXT: li a0, 1 1805; RV64IZBA-NEXT: slli a0, a0, 31 1806; RV64IZBA-NEXT: addi a0, a0, 1365 1807; RV64IZBA-NEXT: ret 1808; 1809; RV64IZBB-LABEL: imm_2147486378: 1810; RV64IZBB: # %bb.0: 1811; RV64IZBB-NEXT: li a0, 1 1812; RV64IZBB-NEXT: slli a0, a0, 31 1813; RV64IZBB-NEXT: addi a0, a0, 1365 1814; RV64IZBB-NEXT: ret 1815; 1816; RV64IZBS-LABEL: imm_2147486378: 1817; RV64IZBS: # %bb.0: 1818; RV64IZBS-NEXT: li a0, 1365 1819; RV64IZBS-NEXT: bseti a0, a0, 31 1820; RV64IZBS-NEXT: ret 1821 ret i64 2147485013 1822} 1823 1824define i64 @imm_neg_2147485013() { 1825; RV32I-LABEL: imm_neg_2147485013: 1826; RV32I: # %bb.0: 1827; RV32I-NEXT: lui a0, 524288 1828; RV32I-NEXT: addi a0, a0, -1365 1829; RV32I-NEXT: li a1, -1 1830; RV32I-NEXT: ret 1831; 1832; RV64I-LABEL: imm_neg_2147485013: 1833; RV64I: # %bb.0: 1834; RV64I-NEXT: lui a0, 524288 1835; RV64I-NEXT: addi a0, a0, -1365 1836; RV64I-NEXT: ret 1837; 1838; RV64IZBA-LABEL: imm_neg_2147485013: 1839; RV64IZBA: # %bb.0: 1840; RV64IZBA-NEXT: lui a0, 524288 1841; RV64IZBA-NEXT: addi a0, a0, -1365 1842; RV64IZBA-NEXT: ret 1843; 1844; RV64IZBB-LABEL: imm_neg_2147485013: 1845; RV64IZBB: # %bb.0: 1846; RV64IZBB-NEXT: lui a0, 524288 1847; RV64IZBB-NEXT: addi a0, a0, -1365 1848; RV64IZBB-NEXT: ret 1849; 1850; RV64IZBS-LABEL: imm_neg_2147485013: 1851; RV64IZBS: # %bb.0: 1852; RV64IZBS-NEXT: lui a0, 524288 1853; RV64IZBS-NEXT: addi a0, a0, -1365 1854; RV64IZBS-NEXT: ret 1855 ret i64 -2147485013 1856} 1857 1858define i64 @imm_12900924131259() { 1859; RV32I-LABEL: imm_12900924131259: 1860; RV32I: # %bb.0: 1861; RV32I-NEXT: lui a0, 765952 1862; RV32I-NEXT: addi a0, a0, 1979 1863; RV32I-NEXT: lui a1, 1 1864; RV32I-NEXT: addi a1, a1, -1093 1865; RV32I-NEXT: ret 1866; 1867; RV64I-LABEL: imm_12900924131259: 1868; RV64I: # %bb.0: 1869; RV64I-NEXT: lui a0, 188 1870; RV64I-NEXT: addiw a0, a0, -1093 1871; RV64I-NEXT: slli a0, a0, 24 1872; RV64I-NEXT: addi a0, a0, 1979 1873; RV64I-NEXT: ret 1874; 1875; RV64IZBA-LABEL: imm_12900924131259: 1876; RV64IZBA: # %bb.0: 1877; RV64IZBA-NEXT: lui a0, 768955 1878; RV64IZBA-NEXT: slli.uw a0, a0, 12 1879; RV64IZBA-NEXT: addi a0, a0, 1979 1880; RV64IZBA-NEXT: ret 1881; 1882; RV64IZBB-LABEL: imm_12900924131259: 1883; RV64IZBB: # %bb.0: 1884; RV64IZBB-NEXT: lui a0, 188 1885; RV64IZBB-NEXT: addiw a0, a0, -1093 1886; RV64IZBB-NEXT: slli a0, a0, 24 1887; RV64IZBB-NEXT: addi a0, a0, 1979 1888; RV64IZBB-NEXT: ret 1889; 1890; RV64IZBS-LABEL: imm_12900924131259: 1891; RV64IZBS: # %bb.0: 1892; RV64IZBS-NEXT: lui a0, 188 1893; RV64IZBS-NEXT: addiw a0, a0, -1093 1894; RV64IZBS-NEXT: slli a0, a0, 24 1895; RV64IZBS-NEXT: addi a0, a0, 1979 1896; RV64IZBS-NEXT: ret 1897 ret i64 12900924131259 1898} 1899 1900define i64 @imm_50394234880() { 1901; RV32I-LABEL: imm_50394234880: 1902; RV32I: # %bb.0: 1903; RV32I-NEXT: lui a0, 768944 1904; RV32I-NEXT: li a1, 11 1905; RV32I-NEXT: ret 1906; 1907; RV64I-LABEL: imm_50394234880: 1908; RV64I: # %bb.0: 1909; RV64I-NEXT: lui a0, 188 1910; RV64I-NEXT: addiw a0, a0, -1093 1911; RV64I-NEXT: slli a0, a0, 16 1912; RV64I-NEXT: ret 1913; 1914; RV64IZBA-LABEL: imm_50394234880: 1915; RV64IZBA: # %bb.0: 1916; RV64IZBA-NEXT: lui a0, 768955 1917; RV64IZBA-NEXT: slli.uw a0, a0, 4 1918; RV64IZBA-NEXT: ret 1919; 1920; RV64IZBB-LABEL: imm_50394234880: 1921; RV64IZBB: # %bb.0: 1922; RV64IZBB-NEXT: lui a0, 188 1923; RV64IZBB-NEXT: addiw a0, a0, -1093 1924; RV64IZBB-NEXT: slli a0, a0, 16 1925; RV64IZBB-NEXT: ret 1926; 1927; RV64IZBS-LABEL: imm_50394234880: 1928; RV64IZBS: # %bb.0: 1929; RV64IZBS-NEXT: lui a0, 188 1930; RV64IZBS-NEXT: addiw a0, a0, -1093 1931; RV64IZBS-NEXT: slli a0, a0, 16 1932; RV64IZBS-NEXT: ret 1933 ret i64 50394234880 1934} 1935 1936define i64 @imm_12900936431479() { 1937; RV32I-LABEL: imm_12900936431479: 1938; RV32I: # %bb.0: 1939; RV32I-NEXT: lui a0, 768955 1940; RV32I-NEXT: addi a0, a0, 1911 1941; RV32I-NEXT: lui a1, 1 1942; RV32I-NEXT: addi a1, a1, -1093 1943; RV32I-NEXT: ret 1944; 1945; RV64I-LABEL: imm_12900936431479: 1946; RV64I: # %bb.0: 1947; RV64I-NEXT: lui a0, 192239 1948; RV64I-NEXT: slli a0, a0, 2 1949; RV64I-NEXT: addi a0, a0, -1093 1950; RV64I-NEXT: slli a0, a0, 12 1951; RV64I-NEXT: addi a0, a0, 1911 1952; RV64I-NEXT: ret 1953; 1954; RV64IZBA-LABEL: imm_12900936431479: 1955; RV64IZBA: # %bb.0: 1956; RV64IZBA-NEXT: lui a0, 768956 1957; RV64IZBA-NEXT: addiw a0, a0, -1093 1958; RV64IZBA-NEXT: slli.uw a0, a0, 12 1959; RV64IZBA-NEXT: addi a0, a0, 1911 1960; RV64IZBA-NEXT: ret 1961; 1962; RV64IZBB-LABEL: imm_12900936431479: 1963; RV64IZBB: # %bb.0: 1964; RV64IZBB-NEXT: lui a0, 192239 1965; RV64IZBB-NEXT: slli a0, a0, 2 1966; RV64IZBB-NEXT: addi a0, a0, -1093 1967; RV64IZBB-NEXT: slli a0, a0, 12 1968; RV64IZBB-NEXT: addi a0, a0, 1911 1969; RV64IZBB-NEXT: ret 1970; 1971; RV64IZBS-LABEL: imm_12900936431479: 1972; RV64IZBS: # %bb.0: 1973; RV64IZBS-NEXT: lui a0, 192239 1974; RV64IZBS-NEXT: slli a0, a0, 2 1975; RV64IZBS-NEXT: addi a0, a0, -1093 1976; RV64IZBS-NEXT: slli a0, a0, 12 1977; RV64IZBS-NEXT: addi a0, a0, 1911 1978; RV64IZBS-NEXT: ret 1979 ret i64 12900936431479 1980} 1981 1982define i64 @imm_12900918536874() { 1983; RV32I-LABEL: imm_12900918536874: 1984; RV32I: # %bb.0: 1985; RV32I-NEXT: lui a0, 764587 1986; RV32I-NEXT: addi a0, a0, -1366 1987; RV32I-NEXT: lui a1, 1 1988; RV32I-NEXT: addi a1, a1, -1093 1989; RV32I-NEXT: ret 1990; 1991; RV64I-LABEL: imm_12900918536874: 1992; RV64I: # %bb.0: 1993; RV64I-NEXT: lui a0, 384477 1994; RV64I-NEXT: addiw a0, a0, 1365 1995; RV64I-NEXT: slli a0, a0, 12 1996; RV64I-NEXT: addi a0, a0, 1365 1997; RV64I-NEXT: slli a0, a0, 1 1998; RV64I-NEXT: ret 1999; 2000; RV64IZBA-LABEL: imm_12900918536874: 2001; RV64IZBA: # %bb.0: 2002; RV64IZBA-NEXT: lui a0, 768955 2003; RV64IZBA-NEXT: addiw a0, a0, -1365 2004; RV64IZBA-NEXT: slli.uw a0, a0, 12 2005; RV64IZBA-NEXT: addi a0, a0, -1366 2006; RV64IZBA-NEXT: ret 2007; 2008; RV64IZBB-LABEL: imm_12900918536874: 2009; RV64IZBB: # %bb.0: 2010; RV64IZBB-NEXT: lui a0, 384477 2011; RV64IZBB-NEXT: addiw a0, a0, 1365 2012; RV64IZBB-NEXT: slli a0, a0, 12 2013; RV64IZBB-NEXT: addi a0, a0, 1365 2014; RV64IZBB-NEXT: slli a0, a0, 1 2015; RV64IZBB-NEXT: ret 2016; 2017; RV64IZBS-LABEL: imm_12900918536874: 2018; RV64IZBS: # %bb.0: 2019; RV64IZBS-NEXT: lui a0, 384477 2020; RV64IZBS-NEXT: addiw a0, a0, 1365 2021; RV64IZBS-NEXT: slli a0, a0, 12 2022; RV64IZBS-NEXT: addi a0, a0, 1365 2023; RV64IZBS-NEXT: slli a0, a0, 1 2024; RV64IZBS-NEXT: ret 2025 ret i64 12900918536874 2026} 2027 2028define i64 @imm_12900925247761() { 2029; RV32I-LABEL: imm_12900925247761: 2030; RV32I: # %bb.0: 2031; RV32I-NEXT: lui a0, 766225 2032; RV32I-NEXT: addi a0, a0, 273 2033; RV32I-NEXT: lui a1, 1 2034; RV32I-NEXT: addi a1, a1, -1093 2035; RV32I-NEXT: ret 2036; 2037; RV64I-LABEL: imm_12900925247761: 2038; RV64I: # %bb.0: 2039; RV64I-NEXT: lui a0, 188 2040; RV64I-NEXT: addiw a0, a0, -1093 2041; RV64I-NEXT: slli a0, a0, 12 2042; RV64I-NEXT: addi a0, a0, 273 2043; RV64I-NEXT: slli a0, a0, 12 2044; RV64I-NEXT: addi a0, a0, 273 2045; RV64I-NEXT: ret 2046; 2047; RV64IZBA-LABEL: imm_12900925247761: 2048; RV64IZBA: # %bb.0: 2049; RV64IZBA-NEXT: lui a0, 768955 2050; RV64IZBA-NEXT: addiw a0, a0, 273 2051; RV64IZBA-NEXT: slli.uw a0, a0, 12 2052; RV64IZBA-NEXT: addi a0, a0, 273 2053; RV64IZBA-NEXT: ret 2054; 2055; RV64IZBB-LABEL: imm_12900925247761: 2056; RV64IZBB: # %bb.0: 2057; RV64IZBB-NEXT: lui a0, 188 2058; RV64IZBB-NEXT: addiw a0, a0, -1093 2059; RV64IZBB-NEXT: slli a0, a0, 12 2060; RV64IZBB-NEXT: addi a0, a0, 273 2061; RV64IZBB-NEXT: slli a0, a0, 12 2062; RV64IZBB-NEXT: addi a0, a0, 273 2063; RV64IZBB-NEXT: ret 2064; 2065; RV64IZBS-LABEL: imm_12900925247761: 2066; RV64IZBS: # %bb.0: 2067; RV64IZBS-NEXT: lui a0, 188 2068; RV64IZBS-NEXT: addiw a0, a0, -1093 2069; RV64IZBS-NEXT: slli a0, a0, 12 2070; RV64IZBS-NEXT: addi a0, a0, 273 2071; RV64IZBS-NEXT: slli a0, a0, 12 2072; RV64IZBS-NEXT: addi a0, a0, 273 2073; RV64IZBS-NEXT: ret 2074 ret i64 12900925247761 2075} 2076 2077define i64 @imm_7158272001() { 2078; RV32I-LABEL: imm_7158272001: 2079; RV32I: # %bb.0: 2080; RV32I-NEXT: lui a0, 699049 2081; RV32I-NEXT: addi a0, a0, 1 2082; RV32I-NEXT: li a1, 1 2083; RV32I-NEXT: ret 2084; 2085; RV64I-LABEL: imm_7158272001: 2086; RV64I: # %bb.0: 2087; RV64I-NEXT: lui a0, 427 2088; RV64I-NEXT: addiw a0, a0, -1367 2089; RV64I-NEXT: slli a0, a0, 12 2090; RV64I-NEXT: addi a0, a0, 1 2091; RV64I-NEXT: ret 2092; 2093; RV64IZBA-LABEL: imm_7158272001: 2094; RV64IZBA: # %bb.0: 2095; RV64IZBA-NEXT: lui a0, 349525 2096; RV64IZBA-NEXT: sh2add a0, a0, a0 2097; RV64IZBA-NEXT: addi a0, a0, 1 2098; RV64IZBA-NEXT: ret 2099; 2100; RV64IZBB-LABEL: imm_7158272001: 2101; RV64IZBB: # %bb.0: 2102; RV64IZBB-NEXT: lui a0, 427 2103; RV64IZBB-NEXT: addiw a0, a0, -1367 2104; RV64IZBB-NEXT: slli a0, a0, 12 2105; RV64IZBB-NEXT: addi a0, a0, 1 2106; RV64IZBB-NEXT: ret 2107; 2108; RV64IZBS-LABEL: imm_7158272001: 2109; RV64IZBS: # %bb.0: 2110; RV64IZBS-NEXT: lui a0, 427 2111; RV64IZBS-NEXT: addiw a0, a0, -1367 2112; RV64IZBS-NEXT: slli a0, a0, 12 2113; RV64IZBS-NEXT: addi a0, a0, 1 2114; RV64IZBS-NEXT: ret 2115 ret i64 7158272001 ; 0x0000_0001_aaaa_9001 2116} 2117 2118define i64 @imm_12884889601() { 2119; RV32I-LABEL: imm_12884889601: 2120; RV32I: # %bb.0: 2121; RV32I-NEXT: lui a0, 1048573 2122; RV32I-NEXT: addi a0, a0, 1 2123; RV32I-NEXT: li a1, 2 2124; RV32I-NEXT: ret 2125; 2126; RV64I-LABEL: imm_12884889601: 2127; RV64I: # %bb.0: 2128; RV64I-NEXT: lui a0, 768 2129; RV64I-NEXT: addiw a0, a0, -3 2130; RV64I-NEXT: slli a0, a0, 12 2131; RV64I-NEXT: addi a0, a0, 1 2132; RV64I-NEXT: ret 2133; 2134; RV64IZBA-LABEL: imm_12884889601: 2135; RV64IZBA: # %bb.0: 2136; RV64IZBA-NEXT: lui a0, 349525 2137; RV64IZBA-NEXT: sh3add a0, a0, a0 2138; RV64IZBA-NEXT: addi a0, a0, 1 2139; RV64IZBA-NEXT: ret 2140; 2141; RV64IZBB-LABEL: imm_12884889601: 2142; RV64IZBB: # %bb.0: 2143; RV64IZBB-NEXT: lui a0, 768 2144; RV64IZBB-NEXT: addiw a0, a0, -3 2145; RV64IZBB-NEXT: slli a0, a0, 12 2146; RV64IZBB-NEXT: addi a0, a0, 1 2147; RV64IZBB-NEXT: ret 2148; 2149; RV64IZBS-LABEL: imm_12884889601: 2150; RV64IZBS: # %bb.0: 2151; RV64IZBS-NEXT: lui a0, 768 2152; RV64IZBS-NEXT: addiw a0, a0, -3 2153; RV64IZBS-NEXT: slli a0, a0, 12 2154; RV64IZBS-NEXT: addi a0, a0, 1 2155; RV64IZBS-NEXT: ret 2156 ret i64 12884889601 ; 0x0000_0002_ffff_d001 2157} 2158 2159define i64 @imm_neg_3435982847() { 2160; RV32I-LABEL: imm_neg_3435982847: 2161; RV32I: # %bb.0: 2162; RV32I-NEXT: lui a0, 209713 2163; RV32I-NEXT: addi a0, a0, 1 2164; RV32I-NEXT: li a1, -1 2165; RV32I-NEXT: ret 2166; 2167; RV64I-LABEL: imm_neg_3435982847: 2168; RV64I: # %bb.0: 2169; RV64I-NEXT: lui a0, 1048371 2170; RV64I-NEXT: addiw a0, a0, 817 2171; RV64I-NEXT: slli a0, a0, 12 2172; RV64I-NEXT: addi a0, a0, 1 2173; RV64I-NEXT: ret 2174; 2175; RV64IZBA-LABEL: imm_neg_3435982847: 2176; RV64IZBA: # %bb.0: 2177; RV64IZBA-NEXT: lui a0, 768955 2178; RV64IZBA-NEXT: sh1add a0, a0, a0 2179; RV64IZBA-NEXT: addi a0, a0, 1 2180; RV64IZBA-NEXT: ret 2181; 2182; RV64IZBB-LABEL: imm_neg_3435982847: 2183; RV64IZBB: # %bb.0: 2184; RV64IZBB-NEXT: lui a0, 1048371 2185; RV64IZBB-NEXT: addiw a0, a0, 817 2186; RV64IZBB-NEXT: slli a0, a0, 12 2187; RV64IZBB-NEXT: addi a0, a0, 1 2188; RV64IZBB-NEXT: ret 2189; 2190; RV64IZBS-LABEL: imm_neg_3435982847: 2191; RV64IZBS: # %bb.0: 2192; RV64IZBS-NEXT: lui a0, 734001 2193; RV64IZBS-NEXT: addiw a0, a0, 1 2194; RV64IZBS-NEXT: bclri a0, a0, 31 2195; RV64IZBS-NEXT: ret 2196 ret i64 -3435982847 ; 0xffff_ffff_3333_1001 2197} 2198 2199define i64 @imm_neg_5726842879() { 2200; RV32I-LABEL: imm_neg_5726842879: 2201; RV32I: # %bb.0: 2202; RV32I-NEXT: lui a0, 698997 2203; RV32I-NEXT: addi a0, a0, 1 2204; RV32I-NEXT: li a1, -2 2205; RV32I-NEXT: ret 2206; 2207; RV64I-LABEL: imm_neg_5726842879: 2208; RV64I: # %bb.0: 2209; RV64I-NEXT: lui a0, 1048235 2210; RV64I-NEXT: addiw a0, a0, -1419 2211; RV64I-NEXT: slli a0, a0, 12 2212; RV64I-NEXT: addi a0, a0, 1 2213; RV64I-NEXT: ret 2214; 2215; RV64IZBA-LABEL: imm_neg_5726842879: 2216; RV64IZBA: # %bb.0: 2217; RV64IZBA-NEXT: lui a0, 768945 2218; RV64IZBA-NEXT: sh2add a0, a0, a0 2219; RV64IZBA-NEXT: addi a0, a0, 1 2220; RV64IZBA-NEXT: ret 2221; 2222; RV64IZBB-LABEL: imm_neg_5726842879: 2223; RV64IZBB: # %bb.0: 2224; RV64IZBB-NEXT: lui a0, 1048235 2225; RV64IZBB-NEXT: addiw a0, a0, -1419 2226; RV64IZBB-NEXT: slli a0, a0, 12 2227; RV64IZBB-NEXT: addi a0, a0, 1 2228; RV64IZBB-NEXT: ret 2229; 2230; RV64IZBS-LABEL: imm_neg_5726842879: 2231; RV64IZBS: # %bb.0: 2232; RV64IZBS-NEXT: lui a0, 698997 2233; RV64IZBS-NEXT: addiw a0, a0, 1 2234; RV64IZBS-NEXT: bclri a0, a0, 32 2235; RV64IZBS-NEXT: ret 2236 ret i64 -5726842879 ; 0xffff_fffe_aaa7_5001 2237} 2238 2239define i64 @imm_neg_10307948543() { 2240; RV32I-LABEL: imm_neg_10307948543: 2241; RV32I: # %bb.0: 2242; RV32I-NEXT: lui a0, 629139 2243; RV32I-NEXT: addi a0, a0, 1 2244; RV32I-NEXT: li a1, -3 2245; RV32I-NEXT: ret 2246; 2247; RV64I-LABEL: imm_neg_10307948543: 2248; RV64I: # %bb.0: 2249; RV64I-NEXT: lui a0, 1047962 2250; RV64I-NEXT: addiw a0, a0, -1645 2251; RV64I-NEXT: slli a0, a0, 12 2252; RV64I-NEXT: addi a0, a0, 1 2253; RV64I-NEXT: ret 2254; 2255; RV64IZBA-LABEL: imm_neg_10307948543: 2256; RV64IZBA: # %bb.0: 2257; RV64IZBA-NEXT: lui a0, 768955 2258; RV64IZBA-NEXT: sh3add a0, a0, a0 2259; RV64IZBA-NEXT: addi a0, a0, 1 2260; RV64IZBA-NEXT: ret 2261; 2262; RV64IZBB-LABEL: imm_neg_10307948543: 2263; RV64IZBB: # %bb.0: 2264; RV64IZBB-NEXT: lui a0, 1047962 2265; RV64IZBB-NEXT: addiw a0, a0, -1645 2266; RV64IZBB-NEXT: slli a0, a0, 12 2267; RV64IZBB-NEXT: addi a0, a0, 1 2268; RV64IZBB-NEXT: ret 2269; 2270; RV64IZBS-LABEL: imm_neg_10307948543: 2271; RV64IZBS: # %bb.0: 2272; RV64IZBS-NEXT: lui a0, 629139 2273; RV64IZBS-NEXT: addiw a0, a0, 1 2274; RV64IZBS-NEXT: bclri a0, a0, 33 2275; RV64IZBS-NEXT: ret 2276 ret i64 -10307948543 ; 0xffff_fffd_9999_3001 2277} 2278 2279define i64 @li_rori_1() { 2280; RV32I-LABEL: li_rori_1: 2281; RV32I: # %bb.0: 2282; RV32I-NEXT: lui a0, 1048567 2283; RV32I-NEXT: addi a1, a0, 2047 2284; RV32I-NEXT: li a0, -1 2285; RV32I-NEXT: ret 2286; 2287; RV64I-LABEL: li_rori_1: 2288; RV64I: # %bb.0: 2289; RV64I-NEXT: li a0, -17 2290; RV64I-NEXT: slli a0, a0, 43 2291; RV64I-NEXT: addi a0, a0, -1 2292; RV64I-NEXT: ret 2293; 2294; RV64IZBA-LABEL: li_rori_1: 2295; RV64IZBA: # %bb.0: 2296; RV64IZBA-NEXT: li a0, -17 2297; RV64IZBA-NEXT: slli a0, a0, 43 2298; RV64IZBA-NEXT: addi a0, a0, -1 2299; RV64IZBA-NEXT: ret 2300; 2301; RV64IZBB-LABEL: li_rori_1: 2302; RV64IZBB: # %bb.0: 2303; RV64IZBB-NEXT: li a0, -18 2304; RV64IZBB-NEXT: rori a0, a0, 21 2305; RV64IZBB-NEXT: ret 2306; 2307; RV64IZBS-LABEL: li_rori_1: 2308; RV64IZBS: # %bb.0: 2309; RV64IZBS-NEXT: li a0, -17 2310; RV64IZBS-NEXT: slli a0, a0, 43 2311; RV64IZBS-NEXT: addi a0, a0, -1 2312; RV64IZBS-NEXT: ret 2313 ret i64 -149533581377537 2314} 2315 2316define i64 @li_rori_2() { 2317; RV32I-LABEL: li_rori_2: 2318; RV32I: # %bb.0: 2319; RV32I-NEXT: lui a0, 720896 2320; RV32I-NEXT: addi a1, a0, -1 2321; RV32I-NEXT: li a0, -6 2322; RV32I-NEXT: ret 2323; 2324; RV64I-LABEL: li_rori_2: 2325; RV64I: # %bb.0: 2326; RV64I-NEXT: li a0, -5 2327; RV64I-NEXT: slli a0, a0, 60 2328; RV64I-NEXT: addi a0, a0, -6 2329; RV64I-NEXT: ret 2330; 2331; RV64IZBA-LABEL: li_rori_2: 2332; RV64IZBA: # %bb.0: 2333; RV64IZBA-NEXT: li a0, -5 2334; RV64IZBA-NEXT: slli a0, a0, 60 2335; RV64IZBA-NEXT: addi a0, a0, -6 2336; RV64IZBA-NEXT: ret 2337; 2338; RV64IZBB-LABEL: li_rori_2: 2339; RV64IZBB: # %bb.0: 2340; RV64IZBB-NEXT: li a0, -86 2341; RV64IZBB-NEXT: rori a0, a0, 4 2342; RV64IZBB-NEXT: ret 2343; 2344; RV64IZBS-LABEL: li_rori_2: 2345; RV64IZBS: # %bb.0: 2346; RV64IZBS-NEXT: li a0, -5 2347; RV64IZBS-NEXT: slli a0, a0, 60 2348; RV64IZBS-NEXT: addi a0, a0, -6 2349; RV64IZBS-NEXT: ret 2350 ret i64 -5764607523034234886 2351} 2352 2353define i64 @li_rori_3() { 2354; RV32I-LABEL: li_rori_3: 2355; RV32I: # %bb.0: 2356; RV32I-NEXT: lui a0, 491520 2357; RV32I-NEXT: addi a0, a0, -1 2358; RV32I-NEXT: li a1, -1 2359; RV32I-NEXT: ret 2360; 2361; RV64I-LABEL: li_rori_3: 2362; RV64I: # %bb.0: 2363; RV64I-NEXT: li a0, -17 2364; RV64I-NEXT: slli a0, a0, 27 2365; RV64I-NEXT: addi a0, a0, -1 2366; RV64I-NEXT: ret 2367; 2368; RV64IZBA-LABEL: li_rori_3: 2369; RV64IZBA: # %bb.0: 2370; RV64IZBA-NEXT: li a0, -17 2371; RV64IZBA-NEXT: slli a0, a0, 27 2372; RV64IZBA-NEXT: addi a0, a0, -1 2373; RV64IZBA-NEXT: ret 2374; 2375; RV64IZBB-LABEL: li_rori_3: 2376; RV64IZBB: # %bb.0: 2377; RV64IZBB-NEXT: li a0, -18 2378; RV64IZBB-NEXT: rori a0, a0, 37 2379; RV64IZBB-NEXT: ret 2380; 2381; RV64IZBS-LABEL: li_rori_3: 2382; RV64IZBS: # %bb.0: 2383; RV64IZBS-NEXT: li a0, -17 2384; RV64IZBS-NEXT: slli a0, a0, 27 2385; RV64IZBS-NEXT: addi a0, a0, -1 2386; RV64IZBS-NEXT: ret 2387 ret i64 -2281701377 2388} 2389 2390; This used to assert when compiled with Zba. 2391define i64 @PR54812() { 2392; RV32I-LABEL: PR54812: 2393; RV32I: # %bb.0: 2394; RV32I-NEXT: lui a0, 521599 2395; RV32I-NEXT: li a1, -1 2396; RV32I-NEXT: ret 2397; 2398; RV64I-LABEL: PR54812: 2399; RV64I: # %bb.0: 2400; RV64I-NEXT: lui a0, 1048447 2401; RV64I-NEXT: addiw a0, a0, 1407 2402; RV64I-NEXT: slli a0, a0, 12 2403; RV64I-NEXT: ret 2404; 2405; RV64IZBA-LABEL: PR54812: 2406; RV64IZBA: # %bb.0: 2407; RV64IZBA-NEXT: lui a0, 872917 2408; RV64IZBA-NEXT: sh1add a0, a0, a0 2409; RV64IZBA-NEXT: ret 2410; 2411; RV64IZBB-LABEL: PR54812: 2412; RV64IZBB: # %bb.0: 2413; RV64IZBB-NEXT: lui a0, 1048447 2414; RV64IZBB-NEXT: addiw a0, a0, 1407 2415; RV64IZBB-NEXT: slli a0, a0, 12 2416; RV64IZBB-NEXT: ret 2417; 2418; RV64IZBS-LABEL: PR54812: 2419; RV64IZBS: # %bb.0: 2420; RV64IZBS-NEXT: lui a0, 1045887 2421; RV64IZBS-NEXT: bclri a0, a0, 31 2422; RV64IZBS-NEXT: ret 2423 ret i64 -2158497792; 2424} 2425