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Searched refs:SPLAT_VECTOR (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp324 EXPECT_EQ(Op->getOpcode(), ISD::SPLAT_VECTOR); in TEST_F()
346 EXPECT_EQ(Val1->getOpcode(), ISD::SPLAT_VECTOR); in TEST_F()
401 EXPECT_EQ(Op->getOpcode(), ISD::SPLAT_VECTOR); in TEST_F()
418 EXPECT_EQ(Val1->getOpcode(), ISD::SPLAT_VECTOR); in TEST_F()
591 EXPECT_EQ(Op.getOpcode(), ISD::SPLAT_VECTOR); in TEST_F()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Disel-splat-vector-dag-crash.ll4 ; for ISD::SPLAT_VECTOR.
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp107 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
108 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
175 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
389 setTargetDAGCombine({ISD::SPLAT_VECTOR, ISD::VSELECT}); in initializeHVXLowering()
1342 SDValue True = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in extendHvxVectorPred()
1681 SDValue Vec1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
1683 SDValue VecW = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
1685 SDValue VecN1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
2436 case ISD::SPLAT_VECTOR: in LowerHvxOperation()
2606 if (Ops[0].getOpcode() == ISD::SPLAT_VECTOR) { in PerformHvxDAGCombine()
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H A DHexagonISelLowering.cpp1647 ISD::SPLAT_VECTOR, in HexagonTargetLowering()
1706 setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal); in HexagonTargetLowering()
2340 case ISD::SPLAT_VECTOR: in getVectorShiftByInt()
2472 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector32()
2535 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector64()
2752 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG)); in getZero()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dconstant-folding.ll14 ; a constant SPLAT_VECTOR didn't follow suit.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h613 SPLAT_VECTOR, enumerator
H A DSelectionDAG.h848 return getNode(ISD::SPLAT_VECTOR, DL, VT, Op);
H A DTargetLowering.h3806 return Op.getOpcode() == ISD::SPLAT_VECTOR; in isTargetCanonicalConstantNode()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp56 case ISD::SPLAT_VECTOR: { in PreprocessISelDAG()
1673 case ISD::SPLAT_VECTOR: in Select()
1681 bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR; in Select()
1697 if (Node->getOpcode() == ISD::SPLAT_VECTOR) in Select()
H A DRISCVISelLowering.cpp489 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
544 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
648 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
810 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
965 ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR}); in RISCVTargetLowering()
3468 case ISD::SPLAT_VECTOR: in LowerOperation()
9310 case ISD::SPLAT_VECTOR: { in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp140 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
312 ISD::SPLAT_VECTOR != Op.getOpcode()) in matchUnaryPredicate()
345 LHS.getOpcode() != ISD::SPLAT_VECTOR)) in matchBinaryPredicate()
2560 case ISD::SPLAT_VECTOR: in isSplatValue()
2772 case ISD::SPLAT_VECTOR: in getSplatSourceVector()
3895 if (Val.getOpcode() == ISD::SPLAT_VECTOR) in isKnownToBeAPowerOfTwo()
5679 Op.getOpcode() == ISD::SPLAT_VECTOR; in FoldConstantArithmetic()
10674 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstOrConstSplat()
10737 if (N.getOpcode() == ISD::SPLAT_VECTOR) in isConstOrConstSplatFP()
11754 if ((N.getOpcode() == ISD::SPLAT_VECTOR) && in isConstantIntBuildVectorOrConstantInt()
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H A DLegalizeVectorOps.cpp943 : ISD::SPLAT_VECTOR, in ExpandSELECT()
1293 !TLI.isOperationLegalOrCustom(ISD::SPLAT_VECTOR, EVLVecVT)))) in ExpandVP_MERGE()
H A DSelectionDAGDumper.cpp298 case ISD::SPLAT_VECTOR: return "splat_vector"; in getOperationName()
H A DDAGCombiner.cpp9290 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
10970 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
11026 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
11028 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
19805 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
20861 return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V); in visitBUILD_VECTOR()
21702 if (V.getOpcode() == ISD::SPLAT_VECTOR) in visitEXTRACT_SUBVECTOR()
23163 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR) in visitINSERT_SUBVECTOR()
23164 return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, N1.getOperand(0)); in visitINSERT_SUBVECTOR()
23508 bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR && in scalarizeBinOpOfSplats()
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H A DLegalizeVectorTypes.cpp964 case ISD::SPLAT_VECTOR: in SplitVectorResult()
1778 StartOfHi = DAG.getNode(ISD::SPLAT_VECTOR, dl, HiVT, StartOfHi); in SplitVecRes_STEP_VECTOR()
1793 assert(N->getOpcode() == ISD::SPLAT_VECTOR && "Unexpected opcode"); in SplitVecRes_ScalarOp()
3665 case ISD::SPLAT_VECTOR: in WidenVectorResult()
H A DTargetLowering.cpp5719 } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildExactSDIV()
5848 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildSDIV()
6005 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildUDIV()
6274 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareUREMEqFold()
6533 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareSREMEqFold()
H A DLegalizeIntegerTypes.cpp123 case ISD::SPLAT_VECTOR: in PromoteIntegerResult()
1641 case ISD::SPLAT_VECTOR: in PromoteIntegerOperand()
4706 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break; in ExpandIntegerOperand()
H A DLegalizeDAG.cpp3797 case ISD::SPLAT_VECTOR: in ExpandNode()
H A DSelectionDAGBuilder.cpp3576 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); in visitShuffleVector()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1141 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1164 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1293 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1355 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1685 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in addTypeForFixedLengthSVE()
5462 case ISD::SPLAT_VECTOR: in LowerOperation()
11753 Op.getOpcode() != ISD::SPLAT_VECTOR && in isPow2Splat()
14877 if (Dup.getOpcode() != ISD::SPLAT_VECTOR) in performSVEAndCombine()
15360 if (V.getOpcode() == ISD::SPLAT_VECTOR) in performExtractSubvectorCombine()
16248 Comparator.getOpcode() == ISD::SPLAT_VECTOR) { in tryConvertSVEWideCompare()
[all …]
H A DAArch64ISelDAGToDAG.cpp184 case ISD::SPLAT_VECTOR: { in SelectDupZeroOrUndef()
204 case ISD::SPLAT_VECTOR: { in SelectDupZero()
245 if (N->getOpcode() != ISD::SPLAT_VECTOR) in SelectSVEShiftSplatImmR()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp849 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR}, in initActions()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td688 def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-int-div.ll1400 ; a SPLAT_VECTOR of fixed vector type should be handled.
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4789 if (N->getOpcode() == ISD::SPLAT_VECTOR) in isZeroVector()