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Searched refs:SOffset (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h166 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
169 SDValue &SOffset, SDValue &Offset) const;
171 SDValue &VAddr, SDValue &SOffset,
196 bool SelectSMRDOffset(SDValue Base, SDValue ByteOffsetNode, SDValue *SOffset,
199 bool SelectSMRDBaseOffset(SDValue Addr, SDValue &SBase, SDValue *SOffset,
201 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue *SOffset,
205 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &SOffset) const;
206 bool SelectSMRDSgprImm(SDValue Addr, SDValue &SBase, SDValue &SOffset,
H A DAMDGPUISelDAGToDAG.cpp1326 SOffset = in SelectMUBUF()
1435 std::tie(VAddr, SOffset) = foldFrameIndex(Addr); in SelectMUBUFScratchOffen()
1462 SOffset = Addr; in SelectMUBUFScratchOffset()
1476 SOffset = Addr.getOperand(0); in SelectMUBUFScratchOffset()
1894 if (!SOffset) in SelectSMRDOffset()
1898 *SOffset = ByteOffsetNode; in SelectSMRDOffset()
1903 *SOffset = ByteOffsetNode.getOperand(0); in SelectSMRDOffset()
1933 if (SOffset) { in SelectSMRDOffset()
1935 *SOffset = SDValue( in SelectSMRDOffset()
1976 if (SOffset && Offset) { in SelectSMRDBaseOffset()
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H A DAMDGPUInstructionSelector.h201 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
272 Register &SOffset, int64_t &ImmOffset) const;
277 Register &RSrcReg, Register &SOffset,
281 Register &SOffset, int64_t &Offset) const;
H A DSIRegisterInfo.cpp896 assert(SOffset->isImm() && SOffset->getImm() == 0); in resolveFrameIndex()
1288 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
1360 SOffset = MCRegister(); in buildSpillLoadStore()
1375 SOffset = Reg; in buildSpillLoadStore()
1382 SOffset = Register(); in buildSpillLoadStore()
1384 if (!SOffset) { in buildSpillLoadStore()
1413 SOffset = ScratchOffsetReg; in buildSpillLoadStore()
1425 if (!UseVGPROffset && !SOffset) in buildSpillLoadStore()
1594 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1631 .addReg(SOffset) in buildSpillLoadStore()
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H A DAMDGPUInstructionSelector.cpp3095 I.add(SOffset); in selectAMDGPU_BUFFER_ATOMIC_FADD()
3938 Register Base, SOffset; in selectSmrdSgpr() local
4673 .addDef(SOffset) in splitIllegalMUBUFOffset()
4758 Register SOffset; in selectMUBUFAddr64() local
4774 if (SOffset) in selectMUBUFAddr64()
4791 Register SOffset; in selectMUBUFOffset() local
4802 if (SOffset) in selectMUBUFOffset()
4818 Register SOffset; in selectMUBUFAddr64Atomic() local
4834 if (SOffset) in selectMUBUFAddr64Atomic()
4851 Register SOffset; in selectMUBUFOffsetAtomic() local
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H A DAMDGPULegalizerInfo.h171 Register SOffset, unsigned ImmOffset, Register VIndex,
H A DAMDGPURegisterBankInfo.cpp1256 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1257 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget, in setBufferOffsets()
1260 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1265 return SOffset + ImmOffset; in setBufferOffsets()
1275 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1276 if ((int)Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
1280 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1287 if (SOffset == 0) { in setBufferOffsets()
1366 Register SOffset; in applyMappingSBufferLoad() local
1371 VOffset, SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
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H A DAMDGPULegalizerInfo.cpp4295 Register VOffset, Register SOffset, in updateBufferMMO() argument
4301 getIConstantVRegValWithLookThrough(SOffset, MRI); in updateBufferMMO()
4439 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
4450 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, MRI); in legalizeBufferStore()
4478 .addUse(SOffset) // soffset in legalizeBufferStore()
4520 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
4537 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, MRI); in legalizeBufferLoad()
4579 .addUse(SOffset) // soffset in legalizeBufferLoad()
4718 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); in legalizeBufferAtomic() local
4725 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, *B.getMRI()); in legalizeBufferAtomic()
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H A DSILoadStoreOptimizer.cpp95 bool SOffset = false; member
560 Result.SOffset = true; in getRegs()
586 Result.SOffset = true; in getRegs()
706 if (Regs.SOffset) in setMI()
H A DGCNHazardRecognizer.cpp811 const MachineOperand *SOffset = in createsVALUHazard() local
816 (!SOffset || !SOffset->isReg())) in createsVALUHazard()
H A DSIInstrInfo.cpp382 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
384 if (SOffset) { in getMemOperandsWithOffsetWidth()
385 if (SOffset->isReg()) in getMemOperandsWithOffsetWidth()
386 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
388 Offset += SOffset->getImm(); in getMemOperandsWithOffsetWidth()
5974 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
5989 .add(*SOffset) in legalizeOperands()
6013 .add(*SOffset) in legalizeOperands()
H A DSIISelLowering.cpp7115 SDValue SOffset, SDValue Offset, in updateBufferMMO() argument
7117 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) || in updateBufferMMO()
7134 cast<ConstantSDNode>(SOffset)->getSExtValue() + in updateBufferMMO()
8457 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
8458 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, in setBufferOffsets()
8461 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
8469 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
8471 if (Offset >= 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
8474 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp724 unsigned SOffset = 0; in getMachineOpValue() local
741 ++SOffset; in getMachineOpValue()
767 : SOffset; in getMachineOpValue()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp331 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
333 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h999 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
H A DAMDGPUBaseInfo.cpp2300 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset() argument
2335 SOffset = Overflow; in splitMUBUFOffset()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4594 StackOffset &SOffset, in isAArch64FrameOffsetLegal() argument
4645 int64_t Offset = IsMulVL ? SOffset.getScalable() : SOffset.getFixed(); in isAArch64FrameOffsetLegal()
4687 SOffset = StackOffset::get(SOffset.getFixed(), Offset); in isAArch64FrameOffsetLegal()
4689 SOffset = StackOffset::get(Offset, SOffset.getScalable()); in isAArch64FrameOffsetLegal()
4691 (SOffset ? 0 : AArch64FrameOffsetIsLegal); in isAArch64FrameOffsetLegal()