3043   MachineOperand &SOffset = MI.getOperand(5);  in selectAMDGPU_BUFFER_ATOMIC_FADD()  local
3095   I.add(SOffset);  in selectAMDGPU_BUFFER_ATOMIC_FADD()
3839                                                  Register *SOffset,  in selectSmrdOffset()  argument
3856   if (SOffset && Offset) {  in selectSmrdOffset()
3864           *SOffset = OffsetReg;  in selectSmrdOffset()
3880   if (SOffset && GEPI.SgprParts.size() == 1 && isUInt<32>(GEPI.Imm) &&  in selectSmrdOffset()
3887     *SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectSmrdOffset()
3888     BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), *SOffset)  in selectSmrdOffset()
3893   if (SOffset && GEPI.SgprParts.size() && GEPI.Imm == 0) {  in selectSmrdOffset()
3896       *SOffset = OffsetReg;  in selectSmrdOffset()
3938   Register Base, SOffset;  in selectSmrdSgpr()  local
3939   if (!selectSmrdOffset(Root, Base, &SOffset, /* Offset= */ nullptr))  in selectSmrdSgpr()
3943            [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); }}};  in selectSmrdSgpr()
3948   Register Base, SOffset;  in selectSmrdSgprImm()  local
3950   if (!selectSmrdOffset(Root, Base, &SOffset, &Offset))  in selectSmrdSgprImm()
3954            [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffset); },  in selectSmrdSgprImm()
4666   MachineIRBuilder &B, Register &SOffset, int64_t &ImmOffset) const {  in splitIllegalMUBUFOffset()  argument
4671   SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);  in splitIllegalMUBUFOffset()
4673     .addDef(SOffset)  in splitIllegalMUBUFOffset()
4680   Register &SOffset, int64_t &Offset) const {  in selectMUBUFAddr64Impl()  argument
4725   splitIllegalMUBUFOffset(B, SOffset, Offset);  in selectMUBUFAddr64Impl()
4730   MachineOperand &Root, Register &RSrcReg, Register &SOffset,  in selectMUBUFOffsetImpl()  argument
4750   splitIllegalMUBUFOffset(B, SOffset, Offset);  in selectMUBUFOffsetImpl()
4758   Register SOffset;  in selectMUBUFAddr64()  local
4761   if (!selectMUBUFAddr64Impl(Root, VAddr, RSrcReg, SOffset, Offset))  in selectMUBUFAddr64()
4774         if (SOffset)  in selectMUBUFAddr64()
4775           MIB.addReg(SOffset);  in selectMUBUFAddr64()
4791   Register SOffset;  in selectMUBUFOffset()  local
4794   if (!selectMUBUFOffsetImpl(Root, RSrcReg, SOffset, Offset))  in selectMUBUFOffset()
4802         if (SOffset)  in selectMUBUFOffset()
4803           MIB.addReg(SOffset);  in selectMUBUFOffset()
4818   Register SOffset;  in selectMUBUFAddr64Atomic()  local
4821   if (!selectMUBUFAddr64Impl(Root, VAddr, RSrcReg, SOffset, Offset))  in selectMUBUFAddr64Atomic()
4834         if (SOffset)  in selectMUBUFAddr64Atomic()
4835           MIB.addReg(SOffset);  in selectMUBUFAddr64Atomic()
4851   Register SOffset;  in selectMUBUFOffsetAtomic()  local
4854   if (!selectMUBUFOffsetImpl(Root, RSrcReg, SOffset, Offset))  in selectMUBUFOffsetAtomic()
4862         if (SOffset)  in selectMUBUFOffsetAtomic()
4863           MIB.addReg(SOffset);  in selectMUBUFOffsetAtomic()