895   MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset);  in resolveFrameIndex()  local
896   assert(SOffset->isImm() && SOffset->getImm() == 0);  in resolveFrameIndex()
1288   MCRegister SOffset = ScratchOffsetReg;  in buildSpillLoadStore()  local
1359   if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) {  in buildSpillLoadStore()
1360     SOffset = MCRegister();  in buildSpillLoadStore()
1367       SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false);  in buildSpillLoadStore()
1375           SOffset = Reg;  in buildSpillLoadStore()
1382       SOffset = Register();  in buildSpillLoadStore()
1384     if (!SOffset) {  in buildSpillLoadStore()
1400     } else if (!SOffset && CanClobberSCC) {  in buildSpillLoadStore()
1413       SOffset = ScratchOffsetReg;  in buildSpillLoadStore()
1425     if (!UseVGPROffset && !SOffset)  in buildSpillLoadStore()
1432       BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), SOffset).addImm(Offset);  in buildSpillLoadStore()
1435       auto Add = BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), SOffset)  in buildSpillLoadStore()
1444   if (IsFlat && SOffset == AMDGPU::NoRegister) {  in buildSpillLoadStore()
1594     if (SOffset == AMDGPU::NoRegister) {  in buildSpillLoadStore()
1605       MIB.addReg(SOffset, SOffsetRegState);  in buildSpillLoadStore()
1630     BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), SOffset)  in buildSpillLoadStore()
1631         .addReg(SOffset)  in buildSpillLoadStore()
2359         auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset);  in eliminateFrameIndex()  local
2360         assert((SOffset.isImm() && SOffset.getImm() == 0));  in eliminateFrameIndex()
2363           SOffset.ChangeToRegister(FrameReg, false);  in eliminateFrameIndex()