Home
last modified time | relevance | path

Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h803 SIGN_EXTEND_VECTOR_INREG, enumerator
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp137 auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
149 auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp71 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
431 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
1003 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorResult()
2752 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorOperand()
3801 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorResult()
4310 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
4437 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4453 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
5584 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
H A DLegalizeVectorOps.cpp389 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
722 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
H A DSelectionDAGDumper.cpp344 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
H A DTargetLowering.cpp826 case ISD::SIGN_EXTEND_VECTOR_INREG: in SimplifyMultipleUseDemandedBits()
2273 case ISD::SIGN_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
2278 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
3252 case ISD::SIGN_EXTEND_VECTOR_INREG: in SimplifyDemandedVectorElts()
H A DSelectionDAG.cpp2673 case ISD::SIGN_EXTEND_VECTOR_INREG: in isSplatValue()
3473 case ISD::SIGN_EXTEND_VECTOR_INREG: { in computeKnownBits()
4069 case ISD::SIGN_EXTEND_VECTOR_INREG: { in ComputeNumSignBits()
5308 case ISD::SIGN_EXTEND_VECTOR_INREG: in getNode()
H A DDAGCombiner.cpp1748 case ISD::SIGN_EXTEND_VECTOR_INREG: in visit()
11326 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in tryToFoldExtendOfConstant()
11392 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
13016 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
13028 TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT))) in visitSIGN_EXTEND_INREG()
13029 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, N00); in visitSIGN_EXTEND_INREG()
22153 Opcode != ISD::SIGN_EXTEND_VECTOR_INREG && in combineTruncationShuffle()
H A DLegalizeIntegerTypes.cpp132 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
5449 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp177 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
252 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp848 ISD::SIGN_EXTEND_VECTOR_INREG, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2359 ISD::SIGN_EXTEND_VECTOR_INREG, in X86TargetLowering()
6928 case ISD::SIGN_EXTEND_VECTOR_INREG: in getOpcode_EXTEND()
6944 case ISD::SIGN_EXTEND_VECTOR_INREG: in getOpcode_EXTEND_VECTOR_INREG()
6945 return ISD::SIGN_EXTEND_VECTOR_INREG; in getOpcode_EXTEND_VECTOR_INREG()
32256 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
46285 if (Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG && in combineMulToPMADDWD()
51708 if (N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) in combineSext()
54521 InOpcode == ISD::SIGN_EXTEND_VECTOR_INREG) && in combineEXTRACT_SUBVECTOR()
54673 LHS.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) && in combinePMULDQ()
54683 RHS.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) && in combinePMULDQ()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp384 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
5799 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
6115 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td439 def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>;