1176     setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);  in X86TargetLowering()
1177     setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);  in X86TargetLowering()
1178     setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);  in X86TargetLowering()
1268       setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal);  in X86TargetLowering()
1494       setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);  in X86TargetLowering()
1767       setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);  in X86TargetLowering()
2359                        ISD::SIGN_EXTEND_VECTOR_INREG,  in X86TargetLowering()
6928   case ISD::SIGN_EXTEND_VECTOR_INREG:  in getOpcode_EXTEND()
6944   case ISD::SIGN_EXTEND_VECTOR_INREG:  in getOpcode_EXTEND_VECTOR_INREG()
6945     return ISD::SIGN_EXTEND_VECTOR_INREG;  in getOpcode_EXTEND_VECTOR_INREG()
22091         Lo = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, MVT::v8i32, In);  in LowerTruncateVecI1()
22095         Hi = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, MVT::v8i32, Hi);  in LowerTruncateVecI1()
25464         Opc == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SIGN_EXTEND  in LowerEXTEND_VECTOR_INREG()
25487   assert(Opc == ISD::SIGN_EXTEND_VECTOR_INREG && "Unexpected opcode!");  in LowerEXTEND_VECTOR_INREG()
25569   SDValue OpLo = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, dl, HalfVT, In);  in LowerSIGN_EXTEND()
25577   OpHi = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, dl, HalfVT, OpHi);  in LowerSIGN_EXTEND()
32256   case ISD::SIGN_EXTEND_VECTOR_INREG:  in LowerOperation()
46285     if (Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG &&  in combineMulToPMADDWD()
46992     unsigned VecInRegOpc = IsSigned ? ISD::SIGN_EXTEND_VECTOR_INREG  in combineVectorPack()
51708     if (N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG)  in combineSext()
54521          InOpcode == ISD::SIGN_EXTEND_VECTOR_INREG) &&  in combineEXTRACT_SUBVECTOR()
54673        LHS.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) &&  in combinePMULDQ()
54683        RHS.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG) &&  in combinePMULDQ()
54732       ISD::LoadExtType Ext = Opcode == ISD::SIGN_EXTEND_VECTOR_INREG  in combineEXTEND_VECTOR_INREG()
55107   case ISD::SIGN_EXTEND_VECTOR_INREG:  in PerformDAGCombine()