| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat32InstrInfo.td | 161 def : PatFPSetcc<SETONE, FCMP_CNE_S, FPR32>;
186 def : PatFPSelectcc<SETONE, FCMP_CNE_S, FSEL_S, FPR32>;
|
| H A D | LoongArchFloat64InstrInfo.td | 165 def : PatFPSetcc<SETONE, FCMP_CNE_D, FPR64>;
186 def : PatFPSelectcc<SETONE, FCMP_CNE_D, FSEL_D, FPR64>;
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1432 SETONE, // 0 1 1 0 True if ordered and operands are unequal enumerator
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 195 case FCmpInst::FCMP_ONE: return ISD::SETONE; in getFCmpCondCode()
212 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
|
| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelDAGToDAG.cpp | 66 case ISD::SETONE: in fpCondCode2Fcc()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 451 case ISD::SETONE: return "setone"; in getOperationName()
|
| H A D | TargetLowering.cpp | 360 case ISD::SETONE: in softenSetCCOperands()
4863 case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break; in SimplifySetCC()
9768 case ISD::SETONE: in LegalizeSetCCCondCode()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructions.td | 326 def COND_ONE : PatFrags<(ops), [(OtherVT SETONE), (OtherVT SETNE)]>;
|
| H A D | R600ISelLowering.cpp | 87 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE, in R600TargetLowering()
897 case ISD::SETONE: in LowerSELECT_CC()
|
| H A D | SIWholeQuadMode.cpp | 874 case ISD::SETONE: in lowerKillF32()
|
| H A D | AMDGPUISelLowering.cpp | 1308 case ISD::SETONE: in combineFMinMaxLegacy()
2046 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFCEIL()
2200 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFFLOOR()
|
| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 112 ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in CSKYTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 855 case ISD::SETONE: in IntCondCCodeToICC()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 300 setCondCodeAction(ISD::SETONE, MVT::v64f16, Expand); in initializeHVXLowering()
313 setCondCodeAction(ISD::SETONE, MVT::v32f32, Expand); in initializeHVXLowering()
|
| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 747 def SETONE : CondCode<"FCMP_ONE">;
1356 (setcc node:$lhs, node:$rhs, SETONE)>;
|
| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 119 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 553 case ISD::SETONE: in getPTXCmpMode()
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1594 case ISD::SETONE: in TranslateM68kCC()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4119 case ISD::SETONE: in getPredicateForSetCC()
4174 case ISD::SETONE: in getCRIdxForSetCC()
|
| H A D | PPCISelLowering.cpp | 662 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in PPCTargetLowering()
663 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); in PPCTargetLowering()
975 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); in PPCTargetLowering()
1028 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand); in PPCTargetLowering()
1201 setCondCodeAction(ISD::SETONE, MVT::f128, Expand); in PPCTargetLowering()
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsMSAInstrInfo.td | 136 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
137 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
|
| H A D | MipsSEISelLowering.cpp | 1831 Op->getOperand(2), ISD::SETONE); in lowerINTRINSIC_WO_CHAIN()
|
| H A D | MipsISelLowering.cpp | 605 case ISD::SETONE: return Mips::FCOND_ONE; in condCodeToFCC()
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1498 case ISD::SETONE: return SPCC::FCC_LG; in FPCondCCodeToFCC()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1346 setCondCodeAction(ISD::SETONE, VT, Expand); in AArch64TargetLowering()
1603 setCondCodeAction(ISD::SETONE, VT, Expand); in addTypeForFixedLengthSVE()
2742 case ISD::SETONE: in changeFPCCToAArch64CC()
2789 case ISD::SETONE: in changeFPCCToANDAArch64CC()
8264 else if ((CC == ISD::SETNE || CC == ISD::SETONE || CC == ISD::SETUNE) && in LowerSELECT_CC()
|