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Searched refs:SETLT (Results 1 – 25 of 61) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1447 SETLT, // 1 X 1 0 0 True if less than enumerator
1458 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp36 case ISD::SETLT: in intCondCode2Icc()
68 case ISD::SETLT: in fpCondCode2Fcc()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp213 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
229 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
252 case ISD::SETLT: in getICmpCondCode()
H A DTargetLoweringBase.cpp682 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
683 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
684 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
685 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; in InitCmpLibcallCCs()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h116 case ISD::SETLT: in getRISCVCCForIntCC()
H A DRISCVInstrInfoZfh.td310 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
316 def : PatSetCC<FPR16, strict_fsetcc, SETLT, PseudoQuietFLT_H>;
334 def : PatSetCC<FPR16, any_fsetccs, SETLT, FLT_H>;
H A DRISCVInstrInfoD.td308 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
314 def : PatSetCC<FPR64, strict_fsetcc, SETLT, PseudoQuietFLT_D>;
332 def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D>;
H A DRISCVInstrInfoVSDPatterns.td690 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
697 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
701 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
712 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLE", SETLT,
960 defm : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
H A DRISCVInstrInfoF.td538 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
544 def : PatSetCC<FPR32, strict_fsetcc, SETLT, PseudoQuietFLT_S>;
562 def : PatSetCC<FPR32, any_fsetccs, SETLT, FLT_S>;
H A DRISCVInstrInfoVVLPatterns.td1066 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
1073 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
1077 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
1085 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
1088 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
1293 defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp584 case ISD::SETLT: in NegateCC()
793 SET_NEWCC(SETLT, JSLT); in EmitInstrWithCustomInserter()
804 CC == ISD::SETLT || in EmitInstrWithCustomInserter()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td367 defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, MVC32>;
416 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
418 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)),
420 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td347 defm : BRCond_Bin<SETLT, "FCMPLT", BT32, MVC32>;
390 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
392 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)),
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp334 case ISD::SETLT: in softenSetCCOperands()
4380 case ISD::SETLT: in SimplifySetCC()
4611 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
4726 ISD::SETLT); in SimplifySetCC()
6654 return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); in getSqrtInputTest()
7444 Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT, in expandFP_TO_UINT()
7448 Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT); in expandFP_TO_UINT()
8846 case ISD::SMIN: CC = ISD::SETLT; break; in expandIntMINMAX()
8972 SatMin, SatMax, ISD::SETLT); in expandShlSat()
9103 ISD::SETLT); in expandFixedPointMul()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3256 case ISD::SETLT: { in get32BitZExtCompare()
3435 case ISD::SETLT: { in get32BitSExtCompare()
3590 case ISD::SETLT: { in get64BitZExtCompare()
3750 case ISD::SETLT: { in get64BitSExtCompare()
4053 case ISD::SETLT: in SelectCC()
4080 case ISD::SETLT: in SelectCC()
4131 case ISD::SETLT: in getPredicateForSetCC()
4337 case ISD::SETLT: { in trySETCC()
4376 case ISD::SETLT: { in trySETCC()
4608 case ISD::SETLT: in mayUseP9Setb()
[all …]
H A DPPCInstrInfo.td3318 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3458 defm : ExtSetCCPat<SETLT,
3490 defm : ExtSetCCPat<SETLT,
3565 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3593 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3605 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3633 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3720 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
3764 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)),
3791 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td76 defm LT_S : ComparisonInt<SETLT, "lt_s", 0x48, 0x53>;
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1503 case ISD::SETLT: in TranslateIntegerM68kCC()
1533 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { in TranslateM68kCC()
1537 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateM68kCC()
1588 case ISD::SETLT: in TranslateM68kCC()
3284 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftLeftParts()
3339 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftRightParts()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td329 def COND_OLT : PatFrags<(ops), [(OtherVT SETOLT), (OtherVT SETLT)]>;
355 def COND_SLT : PatFrag<(ops), (OtherVT SETLT)>;
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td168 def : PatFPSetcc<SETLT, FCMP_CLT_S, FPR32>;
H A DLoongArchISelLowering.cpp260 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT); in lowerShiftLeftParts()
313 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusGRLen, Zero, ISD::SETLT); in lowerShiftRightParts()
H A DLoongArchFloat64InstrInfo.td172 def : PatFPSetcc<SETLT, FCMP_CLT_D, FPR64>;
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp557 case ISD::SETLT: in intCCToAVRCC()
630 CC = ISD::SETLT; in getAVRCmp()
645 CC = ISD::SETLT; in getAVRCmp()
648 case ISD::SETLT: { in getAVRCmp()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1240 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
1257 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
1265 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
1312 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp202 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, in MSP430TargetLowering()
208 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, in MSP430TargetLowering()
1110 case ISD::SETLT: in EmitCMP()

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