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Searched refs:SETGT (Results 1 – 25 of 53) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dunsupported-cc.ll56 ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
91 ; CHECK: SETGT * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x
105 ; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}}
H A Dsetcc.ll158 ; R600: SETGT
186 ; R600: SETGT
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1445 SETGT, // 1 X 0 1 0 True if greater than enumerator
1458 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp38 case ISD::SETGT: in intCondCode2Icc()
71 case ISD::SETGT: in fpCondCode2Fcc()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp215 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
231 case ICmpInst::ICMP_SGT: return ISD::SETGT; in getICmpCondCode()
256 case ISD::SETGT: in getICmpCondCode()
H A DTargetLoweringBase.cpp690 CCs[RTLIB::OGT_F32] = ISD::SETGT; in InitCmpLibcallCCs()
691 CCs[RTLIB::OGT_F64] = ISD::SETGT; in InitCmpLibcallCCs()
692 CCs[RTLIB::OGT_F128] = ISD::SETGT; in InitCmpLibcallCCs()
693 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; in InitCmpLibcallCCs()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3229 case ISD::SETGT: { in get32BitZExtCompare()
3410 case ISD::SETGT: { in get32BitSExtCompare()
3567 case ISD::SETGT: { in get64BitZExtCompare()
3728 case ISD::SETGT: { in get64BitSExtCompare()
4061 case ISD::SETGT: in SelectCC()
4088 case ISD::SETGT: in SelectCC()
4137 case ISD::SETGT: in getPredicateForSetCC()
4219 case ISD::SETGT: in getVCmpInst()
4269 case ISD::SETGT: in getVCmpInst()
4343 case ISD::SETGT: { in trySETCC()
[all …]
H A DPPCInstrInfo.td3374 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3474 defm : ExtSetCCPat<SETGT,
3506 defm : ExtSetCCPat<SETGT,
3569 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3597 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3609 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3637 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3724 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)),
3768 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)),
3795 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)),
[all …]
H A DPPCInstrSPE.td852 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
873 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td368 defm : BRCond_Bin_SWAP_F2<SETGT, "f2FCMPLT", BT32, MVC32>;
428 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)), bb:$imm16),
430 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)),
432 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td348 defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, MVC32>;
398 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)), bb:$imm16),
400 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)),
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp787 SET_NEWCC(SETGT, JSGT); in EmitInstrWithCustomInserter()
802 bool isSignedCmp = (CC == ISD::SETGT || in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td91 [{return (N->getZExtValue() == ISD::SETGT);}]>;
111 [{return (N->getZExtValue() == ISD::SETGT);}]>;
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td78 defm GT_S : ComparisonInt<SETGT, "gt_s", 0x4a, 0x55>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td690 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
697 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
701 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
709 defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGT", SETGT>;
H A DRISCVInstrInfoVVLPatterns.td1066 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
1073 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
1077 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
1085 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
1088 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td327 def COND_OGT : PatFrags<(ops), [(OtherVT SETOGT), (OtherVT SETGT)]>;
353 def COND_SGT : PatFrag<(ops), (OtherVT SETGT)>;
H A DR600Instructions.td746 0x09, "SETGT",
865 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
1722 def : CND_INT_f32 <CNDGT_INT, SETGT>;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1238 X86_INTRINSIC_DATA(sse_comigt_ss, COMI, X86ISD::COMI, ISD::SETGT),
1255 X86_INTRINSIC_DATA(sse_ucomigt_ss, COMI, X86ISD::UCOMI, ISD::SETGT),
1263 X86_INTRINSIC_DATA(sse2_comigt_sd, COMI, X86ISD::COMI, ISD::SETGT),
1310 X86_INTRINSIC_DATA(sse2_ucomigt_sd, COMI, X86ISD::UCOMI, ISD::SETGT),
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp204 { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT }, in MSP430TargetLowering()
210 { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT }, in MSP430TargetLowering()
1107 case ISD::SETGT: in EmitCMP()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp346 case ISD::SETGT: in softenSetCCOperands()
4376 case ISD::SETGT: in SimplifySetCC()
4629 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { in SimplifySetCC()
4734 ISD::SETGT); in SimplifySetCC()
5002 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y in SimplifySetCC()
7387 ISD::SETGT); in expandFP_TO_SINT()
7777 PartialRes = DAG.getSetCC(DL, ResultVT, AbsV, InfV, ISD::SETGT); in expandIS_FPCLASS()
7795 SDValue IsNan = DAG.getSetCC(DL, ResultVT, AbsV, InfV, ISD::SETGT); in expandIS_FPCLASS()
8845 case ISD::SMAX: CC = ISD::SETGT; break; in expandIntMINMAX()
9114 Result = DAG.getSelectCC(dl, Hi, LowMask, SatMax, Result, ISD::SETGT); in expandFixedPointMul()
[all …]
H A DSelectionDAGDumper.cpp463 case ISD::SETGT: return "setgt"; in getOperationName()
H A DLegalizeIntegerTypes.cpp2852 return std::make_pair(ISD::SETGT, ISD::UMAX); in getExpandedMinMaxOps()
3914 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT); in ExpandIntRes_MULFIX()
3927 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT); in ExpandIntRes_MULFIX()
3946 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT); in ExpandIntRes_MULFIX()
4787 (CCCode == ISD::SETGT && CST->isAllOnes())) { // X > -1 in IntegerExpandSetCCOperands()
4799 case ISD::SETGT: in IntegerExpandSetCCOperands()
4869 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp56 case ISD::SETGT: in ISDCCtoARCCC()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1499 case ISD::SETGT: in TranslateIntegerM68kCC()
1528 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { in TranslateM68kCC()
1580 case ISD::SETGT: in TranslateM68kCC()

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