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/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DGISelUtilsTest.cpp18 static const LLT S32 = LLT::scalar(32); variable
50 EXPECT_EQ(S32, getGCDType(S32, S32)); in TEST()
69 EXPECT_EQ(S32, getGCDType(P0, S32)); in TEST()
70 EXPECT_EQ(S32, getGCDType(S32, P0)); in TEST()
134 EXPECT_EQ(S32, getGCDType(S32, V4S8)); in TEST()
158 EXPECT_EQ(S32, getLCMType(S32, S1)); in TEST()
159 EXPECT_EQ(S32, getLCMType(S1, S32)); in TEST()
160 EXPECT_EQ(S32, getLCMType(S32, S32)); in TEST()
162 EXPECT_EQ(S32, getLCMType(S32, S16)); in TEST()
163 EXPECT_EQ(S32, getLCMType(S16, S32)); in TEST()
[all …]
H A DMachineIRBuilderTest.cpp221 LLT S32 = LLT::scalar(32); in TEST_F() local
225 B.buildCTPOP(S32, Copies[0]); in TEST_F()
226 B.buildCTLZ(S32, Copies[0]); in TEST_F()
227 B.buildCTLZ_ZERO_UNDEF(S32, Copies[1]); in TEST_F()
228 B.buildCTTZ(S32, Copies[0]); in TEST_F()
249 LLT S32 = LLT::scalar(32); in TEST_F() local
253 B.buildUITOFP(S32, Copies[0]); in TEST_F()
254 B.buildSITOFP(S32, Copies[0]); in TEST_F()
255 B.buildFPTOUI(S32, Copies[0]); in TEST_F()
256 B.buildFPTOSI(S32, Copies[0]); in TEST_F()
[all …]
H A DLegalizerHelperTest.cpp37 LLT S32 = LLT::scalar(32); in TEST_F() local
147 LLT S32 = LLT::scalar(32); in TEST_F() local
1081 LLT S32 = LLT::scalar(32); in TEST_F() local
2043 LLT S32{LLT::scalar(32)}; in TEST_F() local
2083 LLT S32{LLT::scalar(32)}; in TEST_F() local
2149 LLT S32{LLT::scalar(32)}; in TEST_F() local
2207 LLT S32{LLT::scalar(32)}; in TEST_F() local
2266 LLT S32{LLT::scalar(32)}; in TEST_F() local
2319 LLT S32{LLT::scalar(32)}; in TEST_F() local
2372 LLT S32{LLT::scalar(32)}; in TEST_F() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp661 .legalFor({{S32, S1}, {S32, S32}}) in AMDGPULegalizerInfo()
857 .legalFor({{S32, S32}, {S64, S32}, {S16, S32}}) in AMDGPULegalizerInfo()
868 .legalFor({{S32, S32}, {S32, S64}, {S32, S16}}) in AMDGPULegalizerInfo()
974 .legalFor({{S32, S32}, {S32, S64}}) in AMDGPULegalizerInfo()
975 .clampScalar(0, S32, S32) in AMDGPULegalizerInfo()
987 .clampScalar(0, S32, S32) in AMDGPULegalizerInfo()
995 .legalFor({{S32, S32}, {S32, S64}}) in AMDGPULegalizerInfo()
996 .clampScalar(0, S32, S32) in AMDGPULegalizerInfo()
1387 .legalFor({{S32, S32}, {S64, S32}}); in AMDGPULegalizerInfo()
1672 .legalFor({{S32, S32}}) in AMDGPULegalizerInfo()
[all …]
H A DAMDGPURegisterBankInfo.cpp1472 if (Ty == S32) in applyMappingBFE()
1484 auto UnmergeSOffset = B.buildUnmerge({S32, S32}, ShiftOffset); in applyMappingBFE()
1500 Signed ? B.buildAShr(S32, Extract, B.buildConstant(S32, 31)) : Zero; in applyMappingBFE()
1518 auto ExtShift = B.buildSub(S32, B.buildConstant(S32, 64), WidthReg); in applyMappingBFE()
1538 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16)); in applyMappingBFE()
1734 auto ShiftHi = B.buildAShr(S32, Bitcast, B.buildConstant(S32, 16)); in unpackV2S16ToS32()
1738 auto ShiftHi = B.buildLShr(S32, Bitcast, B.buildConstant(S32, 16)); in unpackV2S16ToS32()
1740 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff)); in unpackV2S16ToS32()
2479 if (Ty == S32) in applyMappingImpl()
2504 if (Ty == S32) in applyMappingImpl()
[all …]
H A DAMDGPUPreLegalizerCombiner.cpp127 const LLT S32 = LLT::scalar(32); in applyClampI64ToI16() local
131 auto Unmerge = B.buildUnmerge(S32, Src); in applyClampI64ToI16()
142 auto MinBoundaryDst = B.buildConstant(S32, MinBoundary); in applyClampI64ToI16()
143 auto MaxBoundaryDst = B.buildConstant(S32, MaxBoundary); in applyClampI64ToI16()
145 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16()
148 AMDGPU::G_AMDGPU_SMED3, {S32}, in applyClampI64ToI16()
H A DAMDGPUPostLegalizerCombiner.cpp189 const LLT S32 = LLT::scalar(32); in applyUCharToFloat() local
195 if (SrcTy != S32) in applyUCharToFloat()
196 SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0); in applyUCharToFloat()
198 if (Ty == S32) { in applyUCharToFloat()
202 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, in applyUCharToFloat()
285 const LLT S32 = LLT::scalar(32); in applyCvtF32UByteN() local
288 if (SrcTy != S32) { in applyCvtF32UByteN()
290 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN()
H A DAMDGPUCallLowering.cpp184 const LLT S32 = LLT::scalar(32); in getStackAddress() local
211 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress()
866 const LLT S32 = LLT::scalar(32); in passSpecialInputs() local
878 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
882 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0); in passSpecialInputs()
888 Register Y = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
892 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0); in passSpecialInputs()
898 Register Z = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
902 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0); in passSpecialInputs()
908 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
[all …]
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DLowLevelTypeTest.cpp135 const LLT S32 = LLT::scalar(32); in TEST() local
144 EXPECT_EQ(S64, S32.changeElementType(S64)); in TEST()
145 EXPECT_EQ(S32, S32.changeElementType(S32)); in TEST()
147 EXPECT_EQ(S32, S64.changeElementSize(32)); in TEST()
148 EXPECT_EQ(S32, S32.changeElementSize(32)); in TEST()
151 EXPECT_EQ(V2S32, V2S64.changeElementType(S32)); in TEST()
156 EXPECT_EQ(P0, S32.changeElementType(P0)); in TEST()
157 EXPECT_EQ(S32, P0.changeElementType(S32)); in TEST()
160 EXPECT_EQ(V2S32, V2P0.changeElementType(S32)); in TEST()
170 EXPECT_EQ(NXV2S32, NXV2S64.changeElementType(S32)); in TEST()
[all …]
/llvm-project-15.0.7/compiler-rt/test/asan/TestCases/
H A Dscariness_score_test.cpp84 struct S32 { struct
144 S32 gm[100];
186 case 5: HeapBuferOverflow<S32>(4, Write); break; in main()
190 case 9: HeapUseAfterFree<S32>(0, Write); break; in main()
206 case 14: StackUseAfterReturn<S32>(0, Write); break; in main()
/llvm-project-15.0.7/mlir/test/Conversion/TosaToArith/
H A Dtosa-to-arith.mlir18 // CHECK-DAG: %[[S32:.+]] = arith.extui %arg2 : i8 to i32
35 // CHECK-DAG: %[[OVER31:.+]] = arith.cmpi sge, %[[S32]], %[[C32]]
36 // CHECK-DAG: %[[OVER32:.+]] = arith.cmpi sgt, %[[S32]], %[[C32]]
37 // CHECK-DAG: %[[HISHLN:.+]] = arith.subi %[[C32]], %[[S32]]
38 // CHECK-DAG: %[[HISHRN:.+]] = arith.subi %[[S32]], %[[C32]]
55 // CHECK-DAG: %[[SHFTM1:.+]] = arith.subi %[[S32]], %[[C1]]
72 // CHECK-DAG: %[[LOR:.+]] = arith.shrui %[[LADD]], %[[S32]]
105 // CHECK-DAG: %[[S32:.+]] = arith.extui %arg2 : i8 to i32
106 // CHECK-DAG: %[[S64:.+]] = arith.extui %[[S32]] : i32 to i64
117 // CHECK-DAG: %[[USED:.+]] = arith.cmpi sgt, %[[S32]], %[[C31]] : i32
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-intrinsics-gfx8.ll17 ; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
18 … = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float [[S32]], <8 x i32> [[RSRC…
30 ; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
32 … = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float [[S32]], float [[T32]], <…
45 ; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
48 … = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 15, float [[S32]], float [[T32]], f…
63 ; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
66 … call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32 15, float [[S32]], float [[T32]], f…
80 ; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
82 …ll <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32 15, float [[S32]], float [[SLICE32]…
[all …]
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dupgrade-datalayout3.ll5 target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
8 …K: target datalayout = "e-m:w-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32-S32"
H A Dupgrade-datalayout4.ll5 …get datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32"
8 …et datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32-a:0:32-S32"
/llvm-project-15.0.7/lld/test/ELF/lto/
H A Damdgcn-oses.ll28 …v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
36 …v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
44 …v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
/llvm-project-15.0.7/llvm/test/Linker/
H A Dcomdat-samesize.ll6 target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
13 target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
H A Dcomdat-largest.ll39 target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
49 target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsABIFlagsSection.cpp25 case FpABIKind::S32: in getFpABIValue()
41 case FpABIKind::S32: in getFpABIString()
/llvm-project-15.0.7/libcxx/test/std/utilities/memory/ptr.align/
H A Dassume_aligned.pass.cpp49 struct alignas( 32) S32 { }; struct
69 S32 s32; in tests()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5968 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); in lowerU64ToF32BitOps()
5969 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); in lowerU64ToF32BitOps()
6034 if (DstTy == S32) { in lowerSITOFP()
6188 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); in lowerFPTRUNC_F64_TO_F16()
6189 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); in lowerFPTRUNC_F64_TO_F16()
6194 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); in lowerFPTRUNC_F64_TO_F16()
6196 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); in lowerFPTRUNC_F64_TO_F16()
6197 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); in lowerFPTRUNC_F64_TO_F16()
6224 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); in lowerFPTRUNC_F64_TO_F16()
6240 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); in lowerFPTRUNC_F64_TO_F16()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-bcc.ll22 %S32 = type <{ i32 }>
23 %Sstruct = type <{ %S64, %S32 }>
/llvm-project-15.0.7/clang/test/PCH/
H A Dcxx-key-functions.cpp40 struct S32 { virtual void f(); }; struct
85 S30, S31, S32, S33, S34, S35, S36, S37, S38, S39,
/llvm-project-15.0.7/llvm/test/Linker/Inputs/
H A Dcomdat-rm-dst.ll1 target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
/llvm-project-15.0.7/lld/test/COFF/Inputs/
H A Dlibcall-archive.ll1 …get datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32"
H A Dlto-lazy-reference-dummy.ll1 …get datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32"

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