Lines Matching refs:S32
184 const LLT S32 = LLT::scalar(32); in getStackAddress() local
211 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress()
866 const LLT S32 = LLT::scalar(32); in passSpecialInputs() local
878 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
882 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0); in passSpecialInputs()
888 Register Y = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
892 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0); in passSpecialInputs()
893 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y; in passSpecialInputs()
898 Register Z = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
902 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0); in passSpecialInputs()
903 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z; in passSpecialInputs()
908 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
922 &AMDGPU::VGPR_32RegClass, S32); in passSpecialInputs()