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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td4428 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
4562 def : Pat<(vnot (AArch64cmeqz VT:$Rn)), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>;
5487 (FADDPv8f16 (FADDPv8f16 V128:$Rn, V128:$Rn), V128:$Rn),
5495 (FADDPv4f32 V128:$Rn, V128:$Rn),
6085 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
6090 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
6094 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
6098 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
6102 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
6106 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
[all …]
H A DAArch64InstrAtomics.td76 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
79 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
92 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
95 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
108 (LDRWui GPR64sp:$Rn, uimm12s4:$offset)>;
111 (LDURWi GPR64sp:$Rn, simm9:$offset)>;
124 (LDRXui GPR64sp:$Rn, uimm12s8:$offset)>;
127 (LDURXi GPR64sp:$Rn, simm9:$offset)>;
138 (LDRSui GPR64sp:$Rn, uimm12s8:$offset)>;
141 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
[all …]
H A DAArch64InstrFormats.td1726 bits<5> Rn;
1740 bits<5> Rn;
1760 bits<5> Rn;
1770 bits<5> Rn;
1789 bits<5> Rn;
2018 bits<5> Rn;
2054 bits<5> Rn;
2082 bits<5> Rn;
2107 bits<5> Rn;
2136 bits<5> Rn;
[all …]
H A DAArch64SchedA64FX.td2313 // [ 5] "addpl $Rd, $Rn, $imm6";
2316 // [ 6] "addvl $Rd, $Rn, $imm6";
2514 // [72] "cpy $Zd, $Pg/m, $Rn";
2526 // [76] "ctermeq $Rn, $Rm";
2529 // [77] "ctermne $Rn, $Rm";
2559 // [87] "dup $Zd, $Rn";
2864 // [189] "index $Zd, $Rn, $Rm";
3873 // [531] "whilele $Pd, $Rn, $Rm";
3876 // [532] "whilelo $Pd, $Rn, $Rm";
3879 // [533] "whilels $Pd, $Rn, $Rm";
[all …]
H A DSVEInstrFormats.td1121 bits<5> Rn;
2545 bits<5> Rn;
4944 bits<5> Rn;
4964 bits<5> Rn;
5011 bits<5> Rn;
5348 bits<5> Rn;
5384 bits<5> Rn;
5712 bits<5> Rn;
5748 bits<5> Rn;
5780 bits<5> Rn;
[all …]
H A DSMEInstrFormats.td274 bits<5> Rn;
283 let Inst{9-5} = Rn;
296 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
451 bits<5> Rn;
460 let Inst{9-5} = Rn;
473 GPR64sp:$Rn, gpr_ty:$Rm),
474 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
580 bits<5> Rn;
587 let Inst{9-5} = Rn;
608 def : InstAlias<opcodestr # "\t$ZAt[$Rv, $imm4], [$Rn]",
[all …]
H A DAArch64InstrGISel.td245 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
246 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
247 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td459 bits<4> Rn;
471 bits<4> Rn;
510 bits<4> Rn;
543 bits<4> Rn;
555 bits<4> Rn;
569 bits<4> Rn;
609 bits<4> Rn;
621 bits<4> Rn;
633 bits<4> Rn;
2487 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;
[all …]
H A DARMInstrInfo.td1840 bits<4> Rn;
1853 bits<4> Rn;
2197 bits<4> Rn;
2733 bits<4> Rn;
3795 bits<4> Rn;
3812 bits<4> Rn;
3909 bits<4> Rn;
4029 bits<4> Rn;
4044 bits<4> Rn;
4062 bits<4> Rn;
[all …]
H A DARMInstrThumb.td828 bits<3> Rn;
856 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
858 bits<3> Rn;
901 bits<3> Rn;
921 bits<3> Rn;
930 bits<3> Rn;
1056 def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
1127 bits<3> Rn;
1145 bits<4> Rn;
1248 bits<3> Rn;
[all …]
H A DARMInstrNEON.td604 let Inst{4} = Rn{4};
677 let Inst{4} = Rn{4};
887 let Inst{4} = Rn{4};
906 let Inst{4} = Rn{4};
1134 let Inst{5} = Rn{4};
1135 let Inst{4} = Rn{4};
1296 let Inst{4} = Rn{4};
1308 let Inst{5} = Rn{5};
1321 let Inst{5} = Rn{5};
1349 let Inst{5} = Rn{5};
[all …]
H A DARMInstrCDE.td84 dag Rn;
136 bits<4> Rn;
140 let Inst{19-16} = Rn{3-0};
154 bits<4> Rn;
159 let Inst{19-16} = Rn{3-0};
170 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);
178 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);
189 let Iops2 = !con(IOpsPrefix, ops.Rn);
190 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
475 let Rn = (ins regclass:$Vn);
[all …]
H A DARMInstrFormats.td804 bits<4> Rn;
822 bits<4> Rn;
934 bits<4> Rn;
965 bits<4> Rn;
987 bits<4> Rn;
1059 bits<4> Rn;
1093 bits<4> Rn;
1518 bits<4> Rn;
1696 bits<4> Rn;
1737 bits<4> Rn;
[all …]
H A DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
20 // | | uopc Rd, Rn, T0 - P01 - 1
23 // and one cycle after the result in Rn is available. The micro-ops can execute
26 // that the resource P01 is needed and that the latency to Rn is different than
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
H A DARMInstrVFP.td242 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
251 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
274 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
287 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
317 NoItinerary, "vlldm${p}\t$Rn", "", []>,
330 NoItinerary, "vlstm${p}\t$Rn", "", []>,
375 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
382 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2862 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> {
2863 bits<4> Rn;
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp2496 if (wback && ((Rn == 15) || (Rn == Rt))) in EmulateSTRRtSP()
3101 uint64_t Rn = in EmulateADDImmThumb() local
3307 if (Rn == 15) in EmulateCMNImm()
3424 if (Rn == 15) in EmulateCMPImm()
3852 Rn = Rd; in EmulateShiftReg()
4235 addr_t Rn = in EmulateLDMDB() local
4347 addr_t Rn = in EmulateLDMIB() local
4461 Rn = 13; in EmulateLDRRtRnImm()
4926 addr_t Rn = in EmulateSTMDB() local
9770 uint32_t Rn; in EmulateTEQImm() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2105 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
2241 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2255 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2274 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2289 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2307 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
5126 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) in DecodeDoubleRegStore()
5151 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; in DecodeLDRPreImm()
5890 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeT2LDRDPreInstruction()
5927 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeT2STRDPreInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp797 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
896 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local
991 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local
1050 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local
1238 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
1248 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeExclusiveLdStInstruction() local
1331 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodePairLdStInstruction() local
1455 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) in DecodePairLdStInstruction()
1487 if (writeback && Rt == Rn && Rn != 31) { in DecodeAuthLoadInstruction()
1857 if (Rd == Rs || Rs == Rn || Rd == Rn) in DecodeCPYMemOpInstruction()
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-thumbv7.txt160 # invalid STRi12 Rn=PC
165 # invalid STRi8 Rn=PC
170 # invalid STRs Rn=PC
175 # invalid STRBi12 Rn=PC
180 # invalid STRBi8 Rn=PC
185 # invalid STRBs Rn=PC
190 # invalid STRHi12 Rn=PC
195 # invalid STRHi8 Rn=PC
200 # invalid STRHs Rn=PC
205 # invalid STRBT Rn=PC
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td213 def : Pat<(i32 (fp_to_sint (round sFPR32Op:$Rn))),
214 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,
216 def : Pat<(i32 (fp_to_uint (round sFPR32Op:$Rn))),
217 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,
219 def : Pat<(i32 (fp_to_sint (round sFPR64Op:$Rn))),
220 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,
222 def : Pat<(i32 (fp_to_uint (round sFPR64Op:$Rn))),
232 def : Pat<(i32 (fp_to_sint sFPR32Op:$Rn)),
235 def : Pat<(i32 (fp_to_uint sFPR32Op:$Rn)),
238 def : Pat<(i32 (fp_to_sint sFPR64Op:$Rn)),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kSchedule.td17 let LoadLatency = 4; // Word (Rn)
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp932 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local
934 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1068 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeRQOpValue() local
1073 return (Rn << 3) | Qm; in getMveAddrModeRQOpValue()
1255 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() local
1274 Binary |= Rn << 13; in getLdStSORegOpValue()
1360 return (Rn << 9) | (1 << 13); in getAddrMode3OpValue()
1362 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode3OpValue() local
1370 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); in getAddrMode3OpValue()
1399 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrModeISOpValue() local
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dzero-reg.ll23 ; instruction (0b11111 in the Rn field would mean "sp").
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp619 const uint32_t Rn = Bits32(opcode, 9, 5); in EmulateADDSUBImm() local
625 const uint32_t n = UInt(Rn); in EmulateADDSUBImm()
699 uint32_t Rn = Bits32(opcode, 9, 5); in EmulateLDPSTP() local
702 integer n = UInt(Rn); in EmulateLDPSTP()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-mul.mir20 ; def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))),
21 ; (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;

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