Lines Matching refs:Rn
544 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
546 [(set DPair:$dst, (v2f64 (word_alignedload GPR:$Rn)))]>;
551 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
553 [(word_alignedstore (v2f64 DPair:$src), GPR:$Rn)]>;
601 (ins AddrMode:$Rn), IIC_VLD1,
602 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD1]> {
604 let Inst{4} = Rn{4};
609 (ins AddrMode:$Rn), IIC_VLD1x2,
610 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD2]> {
612 let Inst{5-4} = Rn{5-4};
629 (ins AddrMode:$Rn), IIC_VLD1u,
630 "vld1", Dt, "$Vd, $Rn!",
631 "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
633 let Inst{4} = Rn{4};
637 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
638 "vld1", Dt, "$Vd, $Rn, $Rm",
639 "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
640 let Inst{4} = Rn{4};
646 (ins AddrMode:$Rn), IIC_VLD1x2u,
647 "vld1", Dt, "$Vd, $Rn!",
648 "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> {
650 let Inst{5-4} = Rn{5-4};
654 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
655 "vld1", Dt, "$Vd, $Rn, $Rm",
656 "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> {
657 let Inst{5-4} = Rn{5-4};
674 (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,
675 "$Vd, $Rn", "", []>, Sched<[WriteVLD3]> {
677 let Inst{4} = Rn{4};
682 (ins AddrMode:$Rn), IIC_VLD1x2u,
683 "vld1", Dt, "$Vd, $Rn!",
684 "$Rn.addr = $wb", []>, Sched<[WriteVLD3]> {
686 let Inst{4} = Rn{4};
690 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
691 "vld1", Dt, "$Vd, $Rn, $Rm",
692 "$Rn.addr = $wb", []>, Sched<[WriteVLD3]> {
693 let Inst{4} = Rn{4};
737 (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,
738 "$Vd, $Rn", "", []>, Sched<[WriteVLD4]> {
740 let Inst{5-4} = Rn{5-4};
745 (ins AddrMode:$Rn), IIC_VLD1x2u,
746 "vld1", Dt, "$Vd, $Rn!",
747 "$Rn.addr = $wb", []>, Sched<[WriteVLD4]> {
749 let Inst{5-4} = Rn{5-4};
753 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
754 "vld1", Dt, "$Vd, $Rn, $Rm",
755 "$Rn.addr = $wb", []>, Sched<[WriteVLD4]> {
756 let Inst{5-4} = Rn{5-4};
801 (ins AddrMode:$Rn), itin,
802 "vld2", Dt, "$Vd, $Rn", "", []> {
804 let Inst{5-4} = Rn{5-4};
830 (ins AddrMode:$Rn), itin,
831 "vld2", Dt, "$Vd, $Rn!",
832 "$Rn.addr = $wb", []> {
834 let Inst{5-4} = Rn{5-4};
838 (ins AddrMode:$Rn, rGPR:$Rm), itin,
839 "vld2", Dt, "$Vd, $Rn, $Rm",
840 "$Rn.addr = $wb", []> {
841 let Inst{5-4} = Rn{5-4};
884 (ins addrmode6:$Rn), IIC_VLD3,
885 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []>, Sched<[WriteVLD3]> {
887 let Inst{4} = Rn{4};
903 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
904 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
905 "$Rn.addr = $wb", []>, Sched<[WriteVLD3]> {
906 let Inst{4} = Rn{4};
943 (ins addrmode6:$Rn), IIC_VLD4,
944 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []>,
947 let Inst{5-4} = Rn{5-4};
963 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
964 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
965 "$Rn.addr = $wb", []>, Sched<[WriteVLD4]> {
966 let Inst{5-4} = Rn{5-4};
1032 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1033 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1036 (i32 (LoadOp addrmode6:$Rn)),
1044 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1045 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1048 (i32 (LoadOp addrmode6oneL32:$Rn)),
1065 let Inst{5-4} = Rn{5-4};
1069 let Inst{5-4} = Rn{5-4};
1118 (ins addrmode6:$Rn, am6offset:$Rm,
1120 "\\{$Vd[$lane]\\}, $Rn$Rm",
1121 "$src = $Vd, $Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
1130 let Inst{4} = Rn{4};
1134 let Inst{5} = Rn{4};
1135 let Inst{4} = Rn{4};
1145 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1146 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1149 let Inst{4} = Rn{4};
1181 (ins addrmode6:$Rn, am6offset:$Rm,
1183 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1184 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1185 let Inst{4} = Rn{4};
1216 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1218 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1253 (ins addrmode6:$Rn, am6offset:$Rm,
1256 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1257 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1290 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1292 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1296 let Inst{4} = Rn{4};
1308 let Inst{5} = Rn{5};
1321 let Inst{5} = Rn{5};
1331 (ins addrmode6:$Rn, am6offset:$Rm,
1334 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1335 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1337 let Inst{4} = Rn{4};
1349 let Inst{5} = Rn{5};
1361 let Inst{5} = Rn{5};
1373 (ins AddrMode:$Rn),
1374 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1376 (Ty (ARMvdup (i32 (LoadOp AddrMode:$Rn)))))]>,
1379 let Inst{4} = Rn{4};
1397 (ins AddrMode:$Rn), IIC_VLD1dup,
1398 "vld1", Dt, "$Vd, $Rn", "",
1400 (Ty (ARMvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1402 let Inst{4} = Rn{4};
1423 (ins AddrMode:$Rn), IIC_VLD1dupu,
1424 "vld1", Dt, "$Vd, $Rn!",
1425 "$Rn.addr = $wb", []> {
1427 let Inst{4} = Rn{4};
1432 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1433 "vld1", Dt, "$Vd, $Rn, $Rm",
1434 "$Rn.addr = $wb", []> {
1435 let Inst{4} = Rn{4};
1442 (ins AddrMode:$Rn), IIC_VLD1dupu,
1443 "vld1", Dt, "$Vd, $Rn!",
1444 "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
1446 let Inst{4} = Rn{4};
1451 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1452 "vld1", Dt, "$Vd, $Rn, $Rm",
1453 "$Rn.addr = $wb", []> {
1454 let Inst{4} = Rn{4};
1470 (ins AddrMode:$Rn), IIC_VLD2dup,
1471 "vld2", Dt, "$Vd, $Rn", "", []> {
1473 let Inst{4} = Rn{4};
1506 (ins AddrMode:$Rn), IIC_VLD2dupu,
1507 "vld2", Dt, "$Vd, $Rn!",
1508 "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
1510 let Inst{4} = Rn{4};
1515 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1516 "vld2", Dt, "$Vd, $Rn, $Rm",
1517 "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
1518 let Inst{4} = Rn{4};
1547 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1548 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []>,
1578 (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1579 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1580 "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> {
1605 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1606 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1608 let Inst{4} = Rn{4};
1614 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1623 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1636 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1637 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1638 "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> {
1639 let Inst{4} = Rn{4};
1645 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1649 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1703 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1704 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST1]> {
1706 let Inst{4} = Rn{4};
1710 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1711 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST2]> {
1713 let Inst{5-4} = Rn{5-4};
1730 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1731 "vst1", Dt, "$Vd, $Rn!",
1732 "$Rn.addr = $wb", []>, Sched<[WriteVST1]> {
1734 let Inst{4} = Rn{4};
1738 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1740 "vst1", Dt, "$Vd, $Rn, $Rm",
1741 "$Rn.addr = $wb", []>, Sched<[WriteVST1]> {
1742 let Inst{4} = Rn{4};
1748 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1749 "vst1", Dt, "$Vd, $Rn!",
1750 "$Rn.addr = $wb", []>, Sched<[WriteVST2]> {
1752 let Inst{5-4} = Rn{5-4};
1756 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1758 "vst1", Dt, "$Vd, $Rn, $Rm",
1759 "$Rn.addr = $wb", []>, Sched<[WriteVST2]> {
1760 let Inst{5-4} = Rn{5-4};
1778 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1779 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST3]> {
1781 let Inst{4} = Rn{4};
1786 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1787 "vst1", Dt, "$Vd, $Rn!",
1788 "$Rn.addr = $wb", []>, Sched<[WriteVST3]> {
1790 let Inst{5-4} = Rn{5-4};
1794 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1796 "vst1", Dt, "$Vd, $Rn, $Rm",
1797 "$Rn.addr = $wb", []>, Sched<[WriteVST3]> {
1798 let Inst{5-4} = Rn{5-4};
1844 (ins AddrMode:$Rn, VecListFourD:$Vd),
1845 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1848 let Inst{5-4} = Rn{5-4};
1853 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1854 "vst1", Dt, "$Vd, $Rn!",
1855 "$Rn.addr = $wb", []>, Sched<[WriteVST4]> {
1857 let Inst{5-4} = Rn{5-4};
1861 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1863 "vst1", Dt, "$Vd, $Rn, $Rm",
1864 "$Rn.addr = $wb", []>, Sched<[WriteVST4]> {
1865 let Inst{5-4} = Rn{5-4};
1911 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1912 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1914 let Inst{5-4} = Rn{5-4};
1940 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1941 "vst2", Dt, "$Vd, $Rn!",
1942 "$Rn.addr = $wb", []>, Sched<[WriteVST2]> {
1944 let Inst{5-4} = Rn{5-4};
1948 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1949 "vst2", Dt, "$Vd, $Rn, $Rm",
1950 "$Rn.addr = $wb", []>, Sched<[WriteVST2]> {
1951 let Inst{5-4} = Rn{5-4};
1957 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1958 "vst2", Dt, "$Vd, $Rn!",
1959 "$Rn.addr = $wb", []>, Sched<[WriteVST4]> {
1961 let Inst{5-4} = Rn{5-4};
1965 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1967 "vst2", Dt, "$Vd, $Rn, $Rm",
1968 "$Rn.addr = $wb", []>, Sched<[WriteVST4]> {
1969 let Inst{5-4} = Rn{5-4};
2009 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
2010 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []>, Sched<[WriteVST3]> {
2012 let Inst{4} = Rn{4};
2027 (ins addrmode6:$Rn, am6offset:$Rm,
2029 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
2030 "$Rn.addr = $wb", []>, Sched<[WriteVST3]> {
2031 let Inst{4} = Rn{4};
2067 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
2068 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
2071 let Inst{5-4} = Rn{5-4};
2086 (ins addrmode6:$Rn, am6offset:$Rm,
2088 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2089 "$Rn.addr = $wb", []>, Sched<[WriteVST4]> {
2090 let Inst{5-4} = Rn{5-4};
2153 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2154 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2155 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]>,
2173 let Inst{4} = Rn{4};
2179 let Inst{5-4} = Rn{5-4};
2202 (ins AdrMode:$Rn, am6offset:$Rm,
2204 "\\{$Vd[$lane]\\}, $Rn$Rm",
2205 "$Rn.addr = $wb",
2207 AdrMode:$Rn, am6offset:$Rm))]>,
2224 let Inst{4} = Rn{4};
2229 let Inst{5-4} = Rn{5-4};
2241 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2242 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2245 let Inst{4} = Rn{4};
2266 let Inst{4} = Rn{4};
2270 let Inst{4} = Rn{4};
2279 (ins addrmode6:$Rn, am6offset:$Rm,
2281 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2282 "$Rn.addr = $wb", []> {
2283 let Inst{4} = Rn{4};
2314 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2316 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []>,
2350 (ins addrmode6:$Rn, am6offset:$Rm,
2353 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2354 "$Rn.addr = $wb", []> {
2385 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2387 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2390 let Inst{4} = Rn{4};
2402 let Inst{5} = Rn{5};
2415 let Inst{5} = Rn{5};
2424 (ins addrmode6:$Rn, am6offset:$Rm,
2427 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2428 "$Rn.addr = $wb", []> {
2429 let Inst{4} = Rn{4};
2441 let Inst{5} = Rn{5};
2453 let Inst{5} = Rn{5};
4363 def : Pat<(v2f32 (fmul DPR:$Rn, (ARMvdup (f32 SPR:$Rm)))),
4364 (VMULslfd DPR:$Rn,
4367 def : Pat<(v4f16 (fmul DPR:$Rn, (ARMvdup (f16 HPR:$Rm)))),
4368 (VMULslhd DPR:$Rn,
4371 def : Pat<(v4f32 (fmul QPR:$Rn, (ARMvdup (f32 SPR:$Rm)))),
4372 (VMULslfq QPR:$Rn,
4375 def : Pat<(v8f16 (fmul QPR:$Rn, (ARMvdup (f16 HPR:$Rm)))),
4376 (VMULslhq QPR:$Rn,
5044 def : Pat<(v4f16 (int_arm_neon_vcadd_rot90 (v4f16 DPR:$Rn), (v4f16 DPR:$Rm))),
5045 (VCADDv4f16 (v4f16 DPR:$Rn), (v4f16 DPR:$Rm), (i32 0))>;
5046 def : Pat<(v4f16 (int_arm_neon_vcadd_rot270 (v4f16 DPR:$Rn), (v4f16 DPR:$Rm))),
5047 (VCADDv4f16 (v4f16 DPR:$Rn), (v4f16 DPR:$Rm), (i32 1))>;
5048 def : Pat<(v8f16 (int_arm_neon_vcadd_rot90 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm))),
5049 (VCADDv8f16 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm), (i32 0))>;
5050 def : Pat<(v8f16 (int_arm_neon_vcadd_rot270 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm))),
5051 (VCADDv8f16 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm), (i32 1))>;
5054 def : Pat<(v2f32 (int_arm_neon_vcadd_rot90 (v2f32 DPR:$Rn), (v2f32 DPR:$Rm))),
5055 (VCADDv2f32 (v2f32 DPR:$Rn), (v2f32 DPR:$Rm), (i32 0))>;
5056 def : Pat<(v2f32 (int_arm_neon_vcadd_rot270 (v2f32 DPR:$Rn), (v2f32 DPR:$Rm))),
5057 (VCADDv2f32 (v2f32 DPR:$Rn), (v2f32 DPR:$Rm), (i32 1))>;
5058 def : Pat<(v4f32 (int_arm_neon_vcadd_rot90 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm))),
5059 (VCADDv4f32 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm), (i32 0))>;
5060 def : Pat<(v4f32 (int_arm_neon_vcadd_rot270 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm))),
5061 (VCADDv4f32 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm), (i32 1))>;
5998 def : Pat<(v8i16 (ARMvshlImm (zext (v8i8 DPR:$Rn)), (i32 8))),
5999 (VSHLLi8 DPR:$Rn, 8)>;
6000 def : Pat<(v4i32 (ARMvshlImm (zext (v4i16 DPR:$Rn)), (i32 16))),
6001 (VSHLLi16 DPR:$Rn, 16)>;
6002 def : Pat<(v2i64 (ARMvshlImm (zext (v2i32 DPR:$Rn)), (i32 32))),
6003 (VSHLLi32 DPR:$Rn, 32)>;
6004 def : Pat<(v8i16 (ARMvshlImm (sext (v8i8 DPR:$Rn)), (i32 8))),
6005 (VSHLLi8 DPR:$Rn, 8)>;
6006 def : Pat<(v4i32 (ARMvshlImm (sext (v4i16 DPR:$Rn)), (i32 16))),
6007 (VSHLLi16 DPR:$Rn, 16)>;
6008 def : Pat<(v2i64 (ARMvshlImm (sext (v2i32 DPR:$Rn)), (i32 32))),
6009 (VSHLLi32 DPR:$Rn, 32)>;
6010 def : Pat<(v8i16 (ARMvshlImm (anyext (v8i8 DPR:$Rn)), (i32 8))),
6011 (VSHLLi8 DPR:$Rn, 8)>;
6012 def : Pat<(v4i32 (ARMvshlImm (anyext (v4i16 DPR:$Rn)), (i32 16))),
6013 (VSHLLi16 DPR:$Rn, 16)>;
6014 def : Pat<(v2i64 (ARMvshlImm (anyext (v2i32 DPR:$Rn)), (i32 32))),
6015 (VSHLLi32 DPR:$Rn, 32)>;
6020 PatFrag<(ops node:$Rn, node:$amt),
6021 (trunc (ARMvshrsImm node:$Rn, node:$amt))>>;
7355 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
7358 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
8097 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
8098 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
8099 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
8100 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;