Lines Matching refs:Rn
1522 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1529 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1530 iii, opc, "\t$Rd, $Rn, $imm",
1531 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1534 bits<4> Rn;
1537 let Inst{19-16} = Rn;
1542 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1543 iir, opc, "\t$Rd, $Rn, $Rm",
1544 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1547 bits<4> Rn;
1551 let Inst{19-16} = Rn;
1558 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1559 iis, opc, "\t$Rd, $Rn, $shift",
1560 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1563 bits<4> Rn;
1566 let Inst{19-16} = Rn;
1574 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1575 iis, opc, "\t$Rd, $Rn, $shift",
1576 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1579 bits<4> Rn;
1582 let Inst{19-16} = Rn;
1595 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1602 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1603 iii, opc, "\t$Rd, $Rn, $imm",
1604 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1607 bits<4> Rn;
1610 let Inst{19-16} = Rn;
1615 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1616 iir, opc, "\t$Rd, $Rn, $Rm",
1620 bits<4> Rn;
1626 let Inst{19-16} = Rn;
1630 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1631 iis, opc, "\t$Rd, $Rn, $shift",
1632 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1635 bits<4> Rn;
1638 let Inst{19-16} = Rn;
1646 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1647 iis, opc, "\t$Rd, $Rn, $shift",
1648 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1651 bits<4> Rn;
1654 let Inst{19-16} = Rn;
1672 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1674 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1677 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1679 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1684 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1686 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1691 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1693 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1704 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1706 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1710 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1713 GPR:$Rn))]>,
1717 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1720 GPR:$Rn))]>,
1733 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1734 opc, "\t$Rn, $imm",
1735 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1737 bits<4> Rn;
1741 let Inst{19-16} = Rn;
1747 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1748 opc, "\t$Rn, $Rm",
1749 [(opnode GPR:$Rn, GPR:$Rm)]>,
1751 bits<4> Rn;
1756 let Inst{19-16} = Rn;
1765 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1766 opc, "\t$Rn, $shift",
1767 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1769 bits<4> Rn;
1773 let Inst{19-16} = Rn;
1782 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1783 opc, "\t$Rn, $shift",
1784 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1786 bits<4> Rn;
1790 let Inst{19-16} = Rn;
1833 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1834 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1835 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1840 bits<4> Rn;
1842 let Inst{19-16} = Rn;
1850 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1851 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1853 bits<4> Rn;
1855 let Inst{19-16} = Rn;
1860 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1864 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1865 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1866 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1870 bits<4> Rn;
1874 let Inst{19-16} = Rn;
1877 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1878 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1879 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1883 bits<4> Rn;
1890 let Inst{19-16} = Rn;
1893 (ins GPR:$Rn, so_reg_imm:$shift),
1894 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1895 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1899 bits<4> Rn;
1902 let Inst{19-16} = Rn;
1909 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1910 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1912 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1916 bits<4> Rn;
1919 let Inst{19-16} = Rn;
1931 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1934 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1935 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1936 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1940 bits<4> Rn;
1944 let Inst{19-16} = Rn;
1947 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1948 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1952 bits<4> Rn;
1958 let Inst{19-16} = Rn;
1960 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1961 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1962 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1966 bits<4> Rn;
1969 let Inst{19-16} = Rn;
1975 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1976 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1977 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1981 bits<4> Rn;
1984 let Inst{19-16} = Rn;
2007 let Inst{19-16} = addr{16-13}; // Rn
2018 let Inst{19-16} = shift{16-13}; // Rn
2038 let Inst{19-16} = addr{16-13}; // Rn
2050 let Inst{19-16} = shift{16-13}; // Rn
2070 let Inst{19-16} = addr{16-13}; // Rn
2081 let Inst{19-16} = shift{16-13}; // Rn
2099 let Inst{19-16} = addr{16-13}; // Rn
2111 let Inst{19-16} = shift{16-13}; // Rn
2192 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2193 "\t$Rd, $Rn, $Rm",
2194 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2197 bits<4> Rn;
2201 let Inst{19-16} = Rn;
2278 let Inst{19-16} = addr{16-13}; // Rn
2294 let Inst{19-16} = shift{16-13}; // Rn
2731 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2733 bits<4> Rn;
2739 let Inst{19-16} = Rn;
2743 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2746 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2749 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2752 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2755 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2758 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2761 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2764 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2937 let Inst{19-16} = addr{12-9}; // Rn
2971 let Inst{19-16} = addr{12-9}; // Rn
3149 let Inst{19-16} = addr{16-13}; // Rn
3162 let Inst{19-16} = addr{16-13}; // Rn
3233 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
3235 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3238 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3240 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3243 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3245 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3248 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3250 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3253 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3255 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
3258 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
3271 let Inst{19-16} = addr{12-9}; // Rn
3304 let Inst{19-16} = addr{12-9}; // Rn
3453 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3455 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3462 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3464 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3473 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3475 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3482 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3484 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3493 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3495 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3502 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3504 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3513 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3515 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3522 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3524 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3551 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3554 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3555 RegConstraint<"$Rn = $wb">;
3729 def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)),
3730 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3731 def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot),
3733 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3775 def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)),
3776 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3777 def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)),
3778 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3790 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3792 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3795 bits<4> Rn;
3803 let Inst{3-0} = Rn;
3807 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3809 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3812 bits<4> Rn;
3820 let Inst{3-0} = Rn;
3847 def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>;
3848 def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>;
3849 def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift),
3850 (SUBSrsi $Rn, so_reg_imm:$shift)>;
3851 def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift),
3852 (SUBSrsr $Rn, so_reg_reg:$shift)>;
3905 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3906 string asm = "\t$Rd, $Rn, $Rm">
3909 bits<4> Rn;
3914 let Inst{19-16} = Rn;
3926 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3927 "\t$Rd, $Rm, $Rn">;
3932 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>;
3943 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>;
3946 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>;
3948 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>;
3951 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
3958 def : ARMV5TEPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
3959 (QDADD rGPR:$Rm, rGPR:$Rn)>;
3960 def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
3961 (QDSUB rGPR:$Rm, rGPR:$Rn)>;
3963 def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
3964 (QADD8 rGPR:$Rm, rGPR:$Rn)>;
3965 def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
3966 (QSUB8 rGPR:$Rm, rGPR:$Rn)>;
3967 def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),
3968 (QADD16 rGPR:$Rm, rGPR:$Rn)>;
3969 def : ARMV6Pat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn),
3970 (QSUB16 rGPR:$Rm, rGPR:$Rn)>;
3981 def : ARMV6Pat<(ARMuqadd8b rGPR:$Rm, rGPR:$Rn),
3982 (UQADD8 rGPR:$Rm, rGPR:$Rn)>;
3983 def : ARMV6Pat<(ARMuqsub8b rGPR:$Rm, rGPR:$Rn),
3984 (UQSUB8 rGPR:$Rm, rGPR:$Rn)>;
3985 def : ARMV6Pat<(ARMuqadd16b rGPR:$Rm, rGPR:$Rn),
3986 (UQADD16 rGPR:$Rm, rGPR:$Rn)>;
3987 def : ARMV6Pat<(ARMuqsub16b rGPR:$Rm, rGPR:$Rn),
3988 (UQSUB16 rGPR:$Rm, rGPR:$Rn)>;
4023 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4025 "\t$Rd, $Rn, $Rm",
4026 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
4029 bits<4> Rn;
4036 let Inst{3-0} = Rn;
4038 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4040 "\t$Rd, $Rn, $Rm, $Ra",
4041 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4044 bits<4> Rn;
4052 let Inst{3-0} = Rn;
4057 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
4058 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
4062 bits<4> Rn;
4070 let Inst{3-0} = Rn;
4074 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
4075 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
4079 bits<4> Rn;
4084 let Inst{3-0} = Rn;
4088 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
4089 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
4093 bits<4> Rn;
4101 let Inst{3-0} = Rn;
4105 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
4106 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
4110 bits<4> Rn;
4115 let Inst{3-0} = Rn;
4122 def : ARMPat<(ARMssat GPRnopc:$Rn, imm0_31:$imm),
4123 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
4124 def : ARMPat<(ARMusat GPRnopc:$Rn, imm0_31:$imm),
4125 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
4138 def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
4139 (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
4140 def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
4141 (SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
4142 def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
4143 (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
4144 def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
4145 (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
4181 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
4183 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
4184 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
4188 bits<4> Rn;
4191 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
4195 let Inst{3-0} = Rn;
4267 bits<4> Rn;
4270 let Inst{3-0} = Rn;
4278 bits<4> Rn;
4282 let Inst{3-0} = Rn;
4290 bits<4> Rn;
4294 let Inst{3-0} = Rn;
4300 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
4302 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4303 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
4304 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
4312 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
4315 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
4316 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
4322 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
4323 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
4324 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
4333 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
4335 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
4336 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
4340 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4341 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
4342 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4347 bits<4> Rn;
4352 let Inst{3-0} = Rn;
4359 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4360 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4362 (smullohi GPR:$Rn, GPR:$Rm))]>,
4367 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4368 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4370 (umullohi GPR:$Rn, GPR:$Rm))]>,
4376 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4379 (smullohi GPR:$Rn, GPR:$Rm))],
4380 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4385 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4388 (umullohi GPR:$Rn, GPR:$Rm))],
4389 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4397 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4398 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4402 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4403 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4408 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4410 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4416 bits<4> Rn;
4420 let Inst{3-0} = Rn;
4426 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4428 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4433 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4435 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4444 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4445 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
4446 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4452 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4453 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
4454 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
4461 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4462 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
4463 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4468 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4469 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
4470 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4475 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4476 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4481 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4482 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
4483 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4488 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4489 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
4490 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
4494 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4495 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4496 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
4500 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4501 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4502 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
4506 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4507 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4508 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
4512 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4513 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4514 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4518 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4519 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4520 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4529 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4530 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4532 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4537 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4538 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4540 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4545 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4546 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4548 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4553 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4554 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4556 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4561 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4562 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4564 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4569 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4570 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4572 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4585 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4586 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4596 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4597 (SMLALBB $Rn, $Rm, $RLo, $RHi)>;
4598 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4599 (SMLALBT $Rn, $Rm, $RLo, $RHi)>;
4600 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4601 (SMLALTB $Rn, $Rm, $RLo, $RHi)>;
4602 def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4603 (SMLALTT $Rn, $Rm, $RLo, $RHi)>;
4610 bits<4> Rn;
4620 let Inst{3-0} = Rn;
4649 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4650 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">,
4654 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4655 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">,
4659 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4661 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
4666 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4668 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
4676 def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4677 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4678 def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4679 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4680 def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4681 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4682 def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4683 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4684 def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4685 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4686 def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4687 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4688 def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4689 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4690 def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4691 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4695 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4696 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">,
4698 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4699 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">,
4706 def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm),
4707 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>;
4708 def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm),
4709 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>;
4710 def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm),
4711 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>;
4712 def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm),
4713 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>;
4718 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4719 "sdiv", "\t$Rd, $Rn, $Rm",
4720 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4724 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4725 "udiv", "\t$Rd, $Rn, $Rm",
4726 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4759 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4760 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4761 def : ARMV6Pat<(srl (bswap top16Zero:$Rn), (i32 16)),
4762 (REV16 GPR:$Rn)>;
4776 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4777 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4778 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4785 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4786 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4787 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4788 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4793 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4794 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4795 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4824 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4825 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4826 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4829 bits<4> Rn;
4836 let Inst{19-16} = Rn;
4897 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4898 "cmn", "\t$Rn, $imm",
4899 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4901 bits<4> Rn;
4905 let Inst{19-16} = Rn;
4913 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4914 "cmn", "\t$Rn, $Rm",
4916 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4917 bits<4> Rn;
4922 let Inst{19-16} = Rn;
4931 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4932 "cmn", "\t$Rn, $shift",
4934 GPR:$Rn, so_reg_imm:$shift)]>,
4936 bits<4> Rn;
4940 let Inst{19-16} = Rn;
4950 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4951 "cmn", "\t$Rn, $shift",
4953 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4955 bits<4> Rn;
4959 let Inst{19-16} = Rn;
5801 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5802 "msr", "\t$mask, $Rn", []> {
5804 bits<4> Rn;
5812 let Inst{3-0} = Rn;
5831 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5832 NoItinerary, "msr", "\t$banked, $Rn", []>,
5835 bits<4> Rn;
5845 let Inst{3-0} = Rn;
6121 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
6122 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
6123 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
6124 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
6130 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
6131 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
6132 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
6133 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
6220 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
6221 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
6223 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
6224 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
6232 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
6233 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
6234 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
6235 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
6239 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
6240 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6241 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
6242 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6243 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
6244 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6252 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
6253 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6254 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
6255 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6256 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
6257 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6310 def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm",
6311 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6316 def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm",
6317 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6324 def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm",
6325 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6329 def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm",
6330 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6335 def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm",
6336 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6339 def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm",
6340 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6371 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
6372 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
6373 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6375 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
6376 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6378 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
6379 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6381 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
6382 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6397 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
6398 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
6400 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
6401 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
6404 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6405 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6407 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6408 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6410 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6411 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6413 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6414 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6422 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
6424 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>;