Lines Matching refs:Rn

231     AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
233           !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
239     AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
242           !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
248     AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
251           !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
259     AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
261           !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
271     AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
274           !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
284     AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
287           !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
316 def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
317                   NoItinerary, "vlldm${p}\t$Rn", "", []>,
329 def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
330                   NoItinerary, "vlstm${p}\t$Rn", "", []>,
367     AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
368           IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
374     AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
375           IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
381     AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
382           IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2860                 !con(iops, (ins t2_addr_offset_none:$Rn,
2862                 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> {
2863    bits<4> Rn;
2864    let Inst{19-16} = Rn{3-0};