| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RegUsageInfoPropagate.cpp | 61 static void setRegMask(MachineInstr &MI, ArrayRef<uint32_t> RegMask) { in setRegMask() argument
62 assert(RegMask.size() == in setRegMask()
69 MO.setRegMask(RegMask.data()); in setRegMask()
122 const ArrayRef<uint32_t> RegMask = PRUI->getRegUsageInfo(F); in runOnMachineFunction() local
123 if (RegMask.empty()) in runOnMachineFunction()
125 setRegMask(MI, RegMask); in runOnMachineFunction()
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| H A D | RegUsageInfoCollector.cpp | 122 std::vector<uint32_t> RegMask; in runOnMachineFunction() local
128 RegMask.resize(RegMaskSize, ~((uint32_t)0)); in runOnMachineFunction()
141 auto SetRegAsDefined = [&RegMask] (unsigned Reg) { in runOnMachineFunction()
142 RegMask[Reg / 32] &= ~(1u << Reg % 32); in runOnMachineFunction()
182 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) in runOnMachineFunction()
189 PRUI.storeUpdateRegUsageInfo(F, RegMask); in runOnMachineFunction()
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| H A D | RegisterUsageInfo.cpp | 58 const Function &FP, ArrayRef<uint32_t> RegMask) { in storeUpdateRegUsageInfo() argument
59 RegMasks[&FP] = RegMask; in storeUpdateRegUsageInfo()
76 for (const auto &RegMask : RegMasks) in print() local
77 FPRMPairVector.push_back(&RegMask); in print()
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| H A D | LiveRegUnits.cpp | 22 void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) { in removeRegsNotPreserved() argument
25 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) in removeRegsNotPreserved()
31 void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) { in addRegsInMask() argument
34 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) in addRegsInMask()
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| H A D | MachineOperand.cpp | 320 const uint32_t *RegMask = getRegMask(); in isIdenticalTo() local
322 if (RegMask == OtherRegMask) in isIdenticalTo()
331 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask); in isIdenticalTo()
907 const uint32_t *RegMask = getRegLiveOut(); in print() local
914 if (RegMask[Reg / 32] & (1U << (Reg % 32))) { in print()
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| H A D | MachineCopyPropagation.cpp | 751 const MachineOperand *RegMask = nullptr; in ForwardCopyPropagateBlock() local
754 RegMask = &MO; in ForwardCopyPropagateBlock()
774 if (RegMask) { in ForwardCopyPropagateBlock()
785 if (!RegMask->clobbersPhysReg(Reg)) { in ForwardCopyPropagateBlock()
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| H A D | MIRPrinter.cpp | 260 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, in printCustomRegMask() argument
262 assert(RegMask && "Can't print an empty register mask"); in printCustomRegMask()
268 if (RegMask[I / 32] & (1u << (I % 32))) { in printCustomRegMask()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 85 RegMask, enumerator
113 uint16_t RegMask; member
265 case Kind::RegMask: in print()
358 if (MemOp.Op == M68kMemOp::Kind::RegMask) in isMoveMask()
373 uint16_t MoveMask = MemOp.RegMask; in addMoveMaskOperands()
837 M68kMemOp MemOp(M68kMemOp::Kind::RegMask); in parseRegOrMoveMask()
838 MemOp.RegMask = 0; in parseRegOrMoveMask()
842 (MemOp.Op == M68kMemOp::Kind::RegMask) && (MemOp.RegMask == 0); in parseRegOrMoveMask()
882 if (MemOp.RegMask == 0) { in parseRegOrMoveMask()
895 if (NewMaskBits & MemOp.RegMask) { in parseRegOrMoveMask()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 173 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut. member
626 static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) { in clobbersPhysReg() argument
629 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); in clobbersPhysReg()
641 return Contents.RegMask; in getRegMask()
652 return Contents.RegMask; in getRegLiveOut()
709 Contents.RegMask = RegMaskPtr; in setRegMask()
898 Op.Contents.RegMask = Mask; in CreateRegMask()
904 Op.Contents.RegMask = Mask; in CreateRegLiveOut()
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| H A D | LiveRegUnits.h | 109 void removeRegsNotPreserved(const uint32_t *RegMask);
113 void addRegsInMask(const uint32_t *RegMask);
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| H A D | RegisterUsageInfo.h | 52 ArrayRef<uint32_t> RegMask);
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| H A D | MachineRegisterInfo.h | 876 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { in addPhysRegsUsedFromRegMask() argument
877 UsedPhysRegMask.setBitsNotInMask(RegMask); in addPhysRegsUsedFromRegMask()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 490 static void handleRegMaskClobber(const uint32_t *RegMask, MCPhysReg Reg, in handleRegMaskClobber() argument
492 if (!MachineOperand::clobbersPhysReg(RegMask, Reg)) in handleRegMaskClobber()
503 const uint32_t *RegMask = MO.getRegMask(); in handleNormalInst() local
505 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst()
507 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallingConv.td | 216 // Trivial class to denote when a def is used only to get a RegMask, i.e.
219 class RegMask<dag mask> : CalleeSavedRegs<mask>;
221 def AMDGPU_AllVGPRs : RegMask<
225 def AMDGPU_AllAGPRs : RegMask<
229 def AMDGPU_AllVectorRegs : RegMask<
233 def AMDGPU_AllAllocatableSRegs : RegMask<
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | statepoint-fastregalloc.mir | 4 # RegMask operand is present. STATEPOINT is an example of such instruction.
23 # Same as above but with multiple RegMask operands per instruction.
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.cpp | 153 const uint32_t *RegMask = getCallPreservedMask(MF, CC); in getReservedRegs() local
154 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) in getReservedRegs()
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| H A D | M68kFrameLowering.cpp | 178 [Reg](MachineBasicBlock::RegisterMaskPair RegMask) { in isRegLiveIn() argument
179 return RegMask.PhysReg == Reg; in isRegLiveIn()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 645 const uint32_t *RegMask; in fuseCompareOperations() local
647 RegMask = MBBI->getOperand(3).getRegMask(); in fuseCompareOperations()
685 MIB.addRegMask(RegMask); in fuseCompareOperations()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 522 unsigned RegMask = MI.getOperand(OpIdx).getImm(); in EncodeMatrixTileListRegisterClass() local
523 assert(RegMask <= 0xFF && "Invalid register mask!"); in EncodeMatrixTileListRegisterClass()
524 return RegMask; in EncodeMatrixTileListRegisterClass()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 583 SmallVectorImpl<int> &RegMask = Dest[I]; in processShuffleMasks() local
584 if (RegMask.empty()) in processShuffleMasks()
589 FirstMask = RegMask; in processShuffleMasks()
593 SecondMask = RegMask; in processShuffleMasks()
597 RegMask.clear(); in processShuffleMasks()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1323 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked() argument
1331 if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue; in CheckForLiveRegDefMasked()
1420 if (const uint32_t *RegMask = getNodeRegMask(Node)) in DelayForLiveRegsBottomUp() local
1421 CheckForLiveRegDefMasked(SU, RegMask, in DelayForLiveRegsBottomUp()
2859 const uint32_t *RegMask = getNodeRegMask(SU->getNode()); in canClobberReachingPhysRegUse() local
2860 if(!ImpDefs && !RegMask) in canClobberReachingPhysRegUse()
2869 if (RegMask && in canClobberReachingPhysRegUse()
2870 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
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| /llvm-project-15.0.7/llvm/tools/llvm-reduce/ |
| H A D | ReducerWorkItem.cpp | 289 if (auto *RegMask = TRI->getCustomEHPadPreservedMask(*DstMF)) in cloneMF() local
290 DstMRI->addPhysRegsUsedFromRegMask(RegMask); in cloneMF()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 1032 for (const MachineBasicBlock::RegisterMaskPair &RegMask : ExitBB->liveins()) { in ValidateLiveOuts() local
1035 if (RegMask.PhysReg == ARM::VPR) { in ValidateLiveOuts()
1041 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
1042 if (auto *MI = RDA.getLocalLiveOutMIDef(Header, RegMask.PhysReg)) in ValidateLiveOuts()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 236 const uint32_t *RegMask = in expandCALL_RVMARKER() local
241 .addRegMask(RegMask) in expandCALL_RVMARKER()
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| H A D | X86RegisterInfo.cpp | 564 const uint32_t *RegMask = getCallPreservedMask(MF, CC); in getReservedRegs() local
565 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) in getReservedRegs()
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