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Searched refs:RegInfo (Results 1 – 25 of 131) sorted by relevance

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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp14 BitVector getAliasedBits(const MCRegisterInfo &RegInfo, in getAliasedBits() argument
16 BitVector AliasedBits(RegInfo.getNumRegs()); in getAliasedBits()
28 : SourceBits(RegInfo.getNumRegs()), AliasedBits(RegInfo.getNumRegs()), in RegisterAliasingTracker()
29 Origins(RegInfo.getNumRegs()) {} in RegisterAliasingTracker()
34 : RegisterAliasingTracker(RegInfo) { in RegisterAliasingTracker()
38 FillOriginAndAliasedBits(RegInfo, SourceBits); in RegisterAliasingTracker()
43 : RegisterAliasingTracker(RegInfo) { in RegisterAliasingTracker()
45 FillOriginAndAliasedBits(RegInfo, SourceBits); in RegisterAliasingTracker()
62 : RegInfo(RegInfo), ReservedReg(ReservedReg), in RegisterAliasingTrackerCache()
63 EmptyRegisters(RegInfo.getNumRegs()) {} in RegisterAliasingTrackerCache()
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H A DRegisterAliasing.h28 BitVector getAliasedBits(const MCRegisterInfo &RegInfo,
43 RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
48 RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
64 RegisterAliasingTracker(const MCRegisterInfo &RegInfo);
67 void FillOriginAndAliasedBits(const MCRegisterInfo &RegInfo,
78 RegisterAliasingTrackerCache(const MCRegisterInfo &RegInfo,
88 const MCRegisterInfo &regInfo() const { return RegInfo; } in regInfo()
97 const MCRegisterInfo &RegInfo;
114 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs);
H A DSnippetFile.cpp35 : MCStreamer(*Context), RegInfo(TheRegInfo), Result(Result) {} in BenchmarkCodeStreamer()
104 for (unsigned I = 0, E = RegInfo->getNumRegs(); I < E; ++I) { in findRegisterByName()
105 if (RegName == RegInfo->getName(I)) in findRegisterByName()
113 const MCRegisterInfo *const RegInfo; member in llvm::exegesis::__anonb84b27170111::BenchmarkCodeStreamer
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/
H A DRegisterAliasingTest.cpp28 const auto &RegInfo = State.getRegInfo(); in TEST_F() local
29 const RegisterAliasingTracker tracker(RegInfo, Mips::T0_64); in TEST_F()
44 const auto &RegInfo = State.getRegInfo(); in TEST_F() local
45 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F()
48 RegInfo, NoReservedReg, in TEST_F()
49 RegInfo.getRegClass( in TEST_F()
52 BitVector sum(RegInfo.getNumRegs()); in TEST_F()
54 sum |= RegisterAliasingTracker(RegInfo, Mips::V0_64).aliasedBits(); in TEST_F()
63 const auto &RegInfo = State.getRegInfo(); in TEST_F() local
64 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F()
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/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DRegisterAliasingTest.cpp29 const auto &RegInfo = State.getRegInfo(); in TEST_F() local
30 const RegisterAliasingTracker tracker(RegInfo, X86::EAX); in TEST_F()
45 const auto &RegInfo = State.getRegInfo(); in TEST_F() local
46 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F()
49 RegInfo, NoReservedReg, RegInfo.getRegClass(X86::GR8_ABCD_LRegClassID)); in TEST_F()
51 BitVector sum(RegInfo.getNumRegs()); in TEST_F()
52 sum |= RegisterAliasingTracker(RegInfo, X86::AL).aliasedBits(); in TEST_F()
53 sum |= RegisterAliasingTracker(RegInfo, X86::BL).aliasedBits(); in TEST_F()
62 const auto &RegInfo = State.getRegInfo(); in TEST_F() local
63 const BitVector NoReservedReg(RegInfo.getNumRegs()); in TEST_F()
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/llvm-project-15.0.7/llvm/lib/MC/
H A DMCInst.cpp21 void MCOperand::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const { in print()
27 if (RegInfo) in print()
28 OS << RegInfo->getName(getReg()); in print()
41 getInst()->print(OS, RegInfo); in print()
72 void MCInst::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const { in print()
76 getOperand(i).print(OS, RegInfo); in print()
83 const MCRegisterInfo *RegInfo) const { in dump_pretty()
85 dump_pretty(OS, InstName, Separator, RegInfo); in dump_pretty()
89 const MCRegisterInfo *RegInfo) const { in dump_pretty()
98 getOperand(i).print(OS, RegInfo); in dump_pretty()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp93 const MipsRegisterInfo &RegInfo; member in __anonfaf8ef210111::ExpandPseudo
102 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
327 &RegInfo, 0); in expandBuildPairF64()
329 &RegInfo, 4); in expandBuildPairF64()
408 const MipsRegisterInfo &RegInfo = in emitPrologue() local
537 if (RegInfo.hasStackRealignment(MF)) { in emitPrologue()
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H A DMipsSERegisterInfo.cpp156 const MipsRegisterInfo *RegInfo = in eliminateFI() local
183 else if (RegInfo->hasStackRealignment(MF)) { in eliminateFI()
224 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in eliminateFI() local
225 Register Reg = RegInfo.createVirtualRegister(PtrRC); in eliminateFI()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp94 const SparcRegisterInfo &RegInfo = in emitPrologue() local
100 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
102 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
151 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue()
164 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue()
165 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue()
256 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
260 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
269 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local
287 } else if (RegInfo->hasStackRealignment(MF)) { in getFrameIndexReference()
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/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp436 return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo); in hasDefOfPhysReg()
443 RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg())) in hasUseOfPhysReg()
447 if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses)) in hasUseOfPhysReg()
463 for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) { in initAliases()
464 BitVector BV(RegInfo->getNumRegs(), false); in initAliases()
471 for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I != E; ++I) { in initAliases()
478 for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I < E; ++I) in initAliases()
483 for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) in initAliases()
485 for (MCSuperRegIterator SI(I, RegInfo); SI.isValid(); ++SI) in initAliases()
511 SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs()); in getRegSize()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallFrameOptimization.cpp114 const X86RegisterInfo &RegInfo,
242 const X86RegisterInfo &RegInfo = in runOnMachineFunction() local
244 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction()
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
345 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
359 const X86RegisterInfo &RegInfo = in collectCallInfo() local
383 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo()
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
H A DX86MachineFunctionInfo.cpp27 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local
29 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp119 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
154 const ThumbRegisterInfo *RegInfo = in emitPrologue() local
169 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
170 Register BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
450 if (RegInfo->hasStackRealignment(MF)) { in emitPrologue()
485 if (RegInfo->hasBasePointer(MF)) in emitPrologue()
507 const ThumbRegisterInfo *RegInfo = in emitEpilogue() local
516 Register FramePtr = RegInfo->getFrameRegister(MF); in emitEpilogue()
639 const ThumbRegisterInfo *RegInfo = in emitPopSpecialFixUp() local
1102 Register FPReg = RegInfo->getFrameRegister(MF); in spillCalleeSavedRegisters()
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H A DARMFrameLowering.cpp1227 if (RegInfo->hasBasePointer(MF)) { in emitPrologue()
1433 if (RegInfo->hasStackRealignment(MF)) { in ResolveFrameIndexReference()
1439 assert(RegInfo->hasBasePointer(MF) && in ResolveFrameIndexReference()
1488 if (RegInfo->hasBasePointer(MF)) { in ResolveFrameIndexReference()
1489 FrameReg = RegInfo->getBaseRegister(); in ResolveFrameIndexReference()
2303 if (RegInfo->hasBasePointer(MF)) in determineCalleeSaves()
2445 if (RegInfo->hasBasePointer(MF)) in determineCalleeSaves()
3084 auto RegInfo = STI.getRegisterInfo(); in adjustForSegmentedStacks() local
3183 auto RegInfo = STI.getRegisterInfo(); in adjustForSegmentedStacks() local
3204 RegInfo->emitLoadConstPool( in adjustForSegmentedStacks()
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/llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/
H A DControlHeightReduction.cpp124 struct RegInfo { struct
125 RegInfo() = default;
192 for (RegInfo &RI : RegInfos) in addSub()
241 for (const RegInfo &RI : RegInfos) in contains()
262 SmallVector<RegInfo, 8> CHRRegions;
431 for (const RegInfo &RI : RegInfos) { in print()
763 RegInfo RI(R); in findScope()
825 RegInfo RI(R); in findScope()
865 RegInfo &RI = Scope->RegInfos[0]; in checkScopeHoistable()
1099 for (RegInfo &RI : Scope->RegInfos) in getSelectsInScope()
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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp314 const VERegisterInfo &RegInfo = *STI.getRegisterInfo(); in emitPrologue() local
316 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
322 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
422 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
426 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
448 const VERegisterInfo *RegInfo = STI.getRegisterInfo(); in getFrameIndexReference() local
459 if (RegInfo->hasStackRealignment(MF) && !isFixed) { in getFrameIndexReference()
470 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp99 const VRegInfo &RegInfo) const;
294 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local
295 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep()
300 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep()
453 const VRegInfo &RegInfo) const { in isUndefRegAtInput()
456 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput()
540 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce() local
541 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in runOnce()
549 if (isUndefRegAtInput(MO, RegInfo)) { in runOnce()
H A DMachineSSAContext.cpp30 RegInfo = &MF->getRegInfo(); in setFunction()
42 auto *MRI = RegInfo; in print()
H A DTargetRegisterInfo.cpp175 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
177 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { in printRegClassOrBank()
178 if (RegInfo.getRegClassOrNull(Reg)) in printRegClassOrBank()
179 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
180 else if (RegInfo.getRegBankOrNull(Reg)) in printRegClassOrBank()
181 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); in printRegClassOrBank()
184 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && in printRegClassOrBank()
H A DTargetFrameLoweringImpl.cpp149 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in allocateScavengingFrameIndexesNearIncomingSP() local
150 return RegInfo->useFPForScavengingIndex(MF) && in allocateScavengingFrameIndexesNearIncomingSP()
151 !RegInfo->hasStackRealignment(MF); in allocateScavengingFrameIndexesNearIncomingSP()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp439 RegInfo->hasStackRealignment(MF)) in hasFP()
864 if (!RegInfo->hasStackRealignment(*MF)) in canUseAsPrologue()
926 if (RegInfo->hasStackRealignment(MF)) in shouldCombineCSRLocalStackBump()
2376 FrameReg = RegInfo->getFrameRegister(MF); in resolveFrameOffsetReference()
2380 FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister() in resolveFrameOffsetReference()
2392 FrameReg = RegInfo->getFrameRegister(MF); in resolveFrameOffsetReference()
2397 if (RegInfo->hasBasePointer(MF)) in resolveFrameOffsetReference()
2398 FrameReg = RegInfo->getBaseRegister(); in resolveFrameOffsetReference()
2989 !RegInfo->isReservedReg(MF, Reg)) { in determineCalleeSaves()
3046 << ' ' << printReg(Reg, RegInfo); in determineCalleeSaves()
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/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.h26 const NVPTXRegisterInfo RegInfo; variable
31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInst.h176 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo = nullptr) const;
228 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo = nullptr) const;
236 const MCRegisterInfo *RegInfo = nullptr) const;
238 const MCRegisterInfo *RegInfo = nullptr) const;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp314 unsigned LR = RegInfo->getRARegister(); in determineFrameLayout()
391 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
535 bool HasBP = RegInfo->hasBasePointer(MF); in twoUniqueScratchRegsRequired()
566 if (!RegInfo || !FI) in stackUpdateCanBeMoved()
643 bool HasBP = RegInfo->hasBasePointer(MF); in emitPrologue()
1250 bool HasBP = RegInfo->hasBasePointer(MF); in inlineStackProbe()
1554 bool HasBP = RegInfo->hasBasePointer(MF); in emitEpilogue()
1973 unsigned LR = RegInfo->getRARegister(); in determineCalleeSaves()
1993 if (!BPSI && RegInfo->hasBasePointer(MF)) { in determineCalleeSaves()
2014 if (RegInfo->hasBasePointer(MF)) in determineCalleeSaves()
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/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterContextPOSIX_s390x.h45 struct RegInfo { struct
55 RegInfo m_reg_info; argument

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