327   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();  in homogeneousPrologEpilog()  local
328   if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF))  in homogeneousPrologEpilog()
428   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();  in hasFP()  local
439       RegInfo->hasStackRealignment(MF))  in hasFP()
861   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in canUseAsPrologue()  local
864   if (!RegInfo->hasStackRealignment(*MF))  in canUseAsPrologue()
899   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in shouldCombineCSRLocalStackBump()  local
926   if (RegInfo->hasStackRealignment(MF))  in shouldCombineCSRLocalStackBump()
989   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in InsertSEH()  local
998     unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
999     unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());  in InsertSEH()
1019                 .addImm(RegInfo->getSEHRegNum(Reg0))  in InsertSEH()
1020                 .addImm(RegInfo->getSEHRegNum(Reg1))  in InsertSEH()
1029     unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1040     unsigned Reg =  RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1049     unsigned Reg0 =  RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1050     unsigned Reg1 =  RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());  in InsertSEH()
1068                 .addImm(RegInfo->getSEHRegNum(Reg0))  in InsertSEH()
1069                 .addImm(RegInfo->getSEHRegNum(Reg1))  in InsertSEH()
1076     int Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1085     unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());  in InsertSEH()
1381   const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();  in emitPrologue()  local
1612       Register FramePtr = RegInfo->getFrameRegister(MF);  in emitPrologue()
1613       unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);  in emitPrologue()
1760         !IsFunclet && RegInfo->hasStackRealignment(MF);  in emitPrologue()
1817   if (!IsFunclet && RegInfo->hasBasePointer(MF)) {  in emitPrologue()
1818     TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,  in emitPrologue()
2054       const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();  in emitEpilogue()  local
2055       unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);  in emitEpilogue()
2190     const AArch64RegisterInfo &RegInfo = *Subtarget.getRegisterInfo();  in emitEpilogue()  local
2191     unsigned Reg = RegInfo.getDwarfRegNum(AArch64::SP, true);  in emitEpilogue()
2260   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(  in getSEHFrameIndexOffset()  local
2263   return RegInfo->getLocalAddressRegister(MF) == AArch64::FP  in getSEHFrameIndexOffset()
2283   const auto *RegInfo = static_cast<const AArch64RegisterInfo *>(  in resolveFrameOffsetReference()  local
2312     } else if (isCSR && RegInfo->hasStackRealignment(MF)) {  in resolveFrameOffsetReference()
2318     } else if (hasFP(MF) && !RegInfo->hasStackRealignment(MF)) {  in resolveFrameOffsetReference()
2330         bool CanUseBP = RegInfo->hasBasePointer(MF);  in resolveFrameOffsetReference()
2343       } else if (MF.hasEHFunclets() && !RegInfo->hasBasePointer(MF)) {  in resolveFrameOffsetReference()
2361       ((isFixed || isCSR) || !RegInfo->hasStackRealignment(MF) || !UseFP) &&  in resolveFrameOffsetReference()
2375                       RegInfo->hasStackRealignment(MF))) {  in resolveFrameOffsetReference()
2376       FrameReg = RegInfo->getFrameRegister(MF);  in resolveFrameOffsetReference()
2380     FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister()  in resolveFrameOffsetReference()
2392     FrameReg = RegInfo->getFrameRegister(MF);  in resolveFrameOffsetReference()
2397   if (RegInfo->hasBasePointer(MF))  in resolveFrameOffsetReference()
2398     FrameReg = RegInfo->getBaseRegister();  in resolveFrameOffsetReference()
2957   const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(  in determineCalleeSaves()  local
2967   unsigned BasePointerReg = RegInfo->hasBasePointer(MF)  in determineCalleeSaves()
2968                                 ? RegInfo->getBaseRegister()  in determineCalleeSaves()
2989           !RegInfo->isReservedReg(MF, Reg)) {  in determineCalleeSaves()
3003           !RegInfo->isReservedReg(MF, PairedReg))  in determineCalleeSaves()
3046              << ' ' << printReg(Reg, RegInfo);  in determineCalleeSaves()
3061   if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))  in determineCalleeSaves()
3072       LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)  in determineCalleeSaves()
3122     MachineFunction &MF, const TargetRegisterInfo *RegInfo,  in assignCalleeSavedSpillSlots()  argument
3152     const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);  in assignCalleeSavedSpillSlots()
3154     unsigned Size = RegInfo->getSpillSize(*RC);  in assignCalleeSavedSpillSlots()
3155     Align Alignment(RegInfo->getSpillAlign(*RC));  in assignCalleeSavedSpillSlots()