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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegister.h20 unsigned Reg; variable
45 return MCRegister::isStackSlot(Reg); in isStackSlot()
92 return isVirtualRegister(Reg); in isVirtual()
98 return isPhysicalRegister(Reg); in isPhysical()
104 return virtReg2Index(Reg); in virtRegIndex()
108 return Reg;
111 unsigned id() const { return Reg; } in id()
114 return MCRegister(Reg); in MCRegister()
123 return MCRegister(Reg); in asMCReg()
129 bool operator==(const Register &Other) const { return Reg == Other.Reg; }
[all …]
H A DMachineRegisterInfo.h123 return MO->Contents.Reg.Next; in getNextOperandForReg()
437 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : ""; in getVRegName()
445 VReg2Name.grow(Reg); in insertVRegByName()
446 VReg2Name[Reg] = Name.str(); in insertVRegByName()
459 def_iterator DI = def_begin(Reg); in getOneDef()
677 return VRegInfo[Reg].first; in getRegClassOrRegBank()
688 VRegInfo[Reg].first = RCOrRB; in setRegClassOrRegBank()
740 LLT getType(Register Reg) const { in getType() argument
741 if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg)) in getType()
742 return VRegToType[Reg]; in getType()
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H A DLiveVariables.h157 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
158 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
164 MachineInstr *FindLastRefOrPartRef(Register Reg);
169 MachineInstr *FindLastPartialDef(Register Reg,
196 void recomputeForSingleDefVirtReg(Register Reg);
218 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterKilled()
253 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterDead()
277 VarInfo &getVarInfo(Register Reg);
289 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); in isLiveIn()
311 bool isPHIJoin(Register Reg) { return PHIJoins.test(Reg.id()); } in isPHIJoin() argument
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H A DLiveIntervals.h113 if (hasInterval(Reg)) in getInterval()
114 return *VirtRegIntervals[Reg.id()]; in getInterval()
123 bool hasInterval(Register Reg) const { in hasInterval() argument
125 VirtRegIntervals[Reg.id()]; in hasInterval()
131 VirtRegIntervals.grow(Reg.id()); in createEmptyInterval()
132 VirtRegIntervals[Reg.id()] = createInterval(Reg); in createEmptyInterval()
133 return *VirtRegIntervals[Reg.id()]; in createEmptyInterval()
143 void removeInterval(Register Reg) { in removeInterval() argument
144 delete VirtRegIntervals[Reg]; in removeInterval()
145 VirtRegIntervals[Reg] = nullptr; in removeInterval()
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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dload.ll29 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
34 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
35 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
41 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
44 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
46 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
47 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
66 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
69 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
70 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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H A Dstore.ll28 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
33 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
34 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
40 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
43 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
45 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
46 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
65 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
68 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
69 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
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H A Dfptosi.ll42 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
43 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
45 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
47 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
48 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
118 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
119 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
121 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
123 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
124 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp58 VRegInfo[Reg].first = RC; in setRegClass()
86 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
146 VRegInfo.grow(Reg); in createIncompleteVirtualRegister()
149 return Reg; in createIncompleteVirtualRegister()
167 return Reg; in createVirtualRegister()
177 return Reg; in cloneVirtualRegister()
191 setType(Reg, Ty); in createGenericVirtualRegister()
194 return Reg; in createGenericVirtualRegister()
206 verifyUseList(Reg); in clearVirtRegs()
434 if ((Register)LI.first == Reg || LI.second == Reg) in isLiveIn()
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H A DAggressiveAntiDepBreaker.cpp83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
85 Regs.push_back(Reg); in GetGroupRegs()
117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
172 unsigned Reg = *I; in StartBlock() local
203 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
212 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
229 if (Reg == 0) in IsImplicitDefUse()
314 RegRefs.erase(Reg); in HandleLastUse()
565 SuperReg = Reg; in FindSuitableFreeRegisters()
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H A DLiveVariables.cpp86 VirtRegInfo.grow(Reg); in getVarInfo()
87 return VirtRegInfo[Reg]; in getVarInfo()
361 if (!PhysRegUse[Reg]) { in HandlePhysRegKill()
366 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill()
423 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { in HandleRegMask() local
425 if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) in HandleRegMask()
444 if (PhysRegDef[Reg] || PhysRegUse[Reg]) { in HandlePhysRegDef()
649 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) in runOnMachineFunction()
650 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI); in runOnMachineFunction()
652 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI); in runOnMachineFunction()
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H A DCriticalAntiDepBreaker.cpp70 unsigned Reg = *AI; in StartBlock() local
84 unsigned Reg = *I; in StartBlock() local
88 unsigned Reg = *AI; in StartBlock() local
91 DefIndices[Reg] = ~0u; in StartBlock()
114 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
121 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { in Observe()
185 if (Reg == 0) continue; in PrescanInstruction()
194 Classes[Reg] = NewRC; in PrescanInstruction()
227 if (!Reg.isValid()) in PrescanInstruction()
318 if (Reg == 0) continue; in ScanInstruction()
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H A DFixupStatepointCallerSaved.cpp118 return Reg; in performCopyPropagation()
122 return Reg; in performCopyPropagation()
137 return Reg; in performCopyPropagation()
141 return Reg; in performCopyPropagation()
146 return Reg; in performCopyPropagation()
257 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex()
367 bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; } in isCalleeSaved() argument
391 if (isCalleeSaved(Reg) && (AllowGCPtrInCSR || !is_contained(GCRegs, Reg))) in findRegistersToSpill()
421 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters()
462 if (EHPad && !RC.hasReload(Reg, RegToSlotIdx[Reg], EHPad)) { in insertReloads()
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H A DRegisterScavenging.cpp75 SI.Reg = 0; in init()
172 I.Reg = 0; in forward()
187 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg)) in forward()
226 assert((KillRegs.test(Reg) || isUnused(Reg) || in forward()
248 I.Reg = 0; in backward()
271 return Reg; in FindUnusedReg()
382 if (!MRI.isReserved(Reg) && Used.available(Reg) && in findSurvivorBackwards()
400 if (!MRI.isReserved(Reg) && Used.available(Reg)) { in findSurvivorBackwards()
488 Scavenged[SI].Reg = Reg; in spill()
604 return Reg; in scavengeRegisterBackwards()
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H A DLivePhysRegs.cpp88 if (!Reg.isPhysical()) in stepForward()
97 removeReg(Reg); in stepForward()
108 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
111 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first)) in stepForward()
113 addReg(Reg.first); in stepForward()
143 if (LiveRegs.count(Reg)) in available()
145 if (MRI.isReserved(Reg)) in available()
162 addReg(Reg); in addBlockLiveIns()
277 MBB.addLiveIn(Reg); in addLiveIns()
299 if (Reg == 0) in recomputeLivenessFlags()
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H A DMachineInstrBundle.cpp161 Register Reg = MO.getReg(); in finalizeBundle() local
162 if (!Reg) in finalizeBundle()
184 Register Reg = MO.getReg(); in finalizeBundle() local
185 if (!Reg) in finalizeBundle()
189 LocalDefs.push_back(Reg); in finalizeBundle()
191 DeadDefSet.insert(Reg); in finalizeBundle()
195 KilledDefSet.erase(Reg); in finalizeBundle()
198 DeadDefSet.erase(Reg); in finalizeBundle()
215 Register Reg = LocalDefs[i]; in finalizeBundle() local
218 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg); in finalizeBundle()
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H A DRDFRegisters.cpp49 if (UnitInfos[U].Reg != 0) in PhysicalRegisterInfo()
57 UnitInfos[U].Reg = F; in PhysicalRegisterInfo()
62 UI.Reg = F; in PhysicalRegisterInfo()
109 assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg)); in getAliasSet()
110 if (isRegMaskId(Reg)) { in getAliasSet()
120 if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
168 assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); in aliasRM()
170 bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); in aliasRM()
203 assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg)); in aliasMM()
231 if (RR.Reg == R) in mapTo()
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/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegister.h26 unsigned Reg; variable
29 constexpr MCRegister(unsigned Val = 0): Reg(Val) {} in Reg() function
52 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
53 return FirstStackSlot <= Reg && Reg < VirtualRegFlag; in isStackSlot()
58 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
59 return FirstPhysicalReg <= Reg && Reg < FirstStackSlot; in isPhysicalRegister()
63 return Reg;
73 return Reg; in id()
79 bool operator==(const MCRegister &Other) const { return Reg == Other.Reg; }
80 bool operator!=(const MCRegister &Other) const { return Reg != Other.Reg; }
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H A DMCRegisterInfo.h69 unsigned RegNo = unsigned(Reg); in contains()
253 Iter.init(Reg, DiffList); in mc_difflist_iterator()
291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} in mc_subreg_iterator()
303 : mc_difflist_iterator(Reg, in mc_superreg_iterator()
339 return concat<const MCPhysReg>(subregs_inclusive(Reg), superregs(Reg)); in sub_and_superregs_inclusive()
601 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
618 : SRIter(Reg, MCRI) { in MCSubRegIndexIterator()
650 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
724 : RUIter(Reg, MCRI) { in MCRegUnitMaskIterator()
790 MCRegister Reg;
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
113 if (isVecReg(Reg)) in getInstrVecReg()
119 if (isVecReg(Reg)) in getInstrVecReg()
125 if (isVecReg(Reg)) in getInstrVecReg()
168 unsigned Reg = 0; in runOnMachineFunction() local
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction()
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/llvm-project-15.0.7/llvm/test/MC/Lanai/
H A Dmemory.s10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
34 ! CHECK-NEXT: <MCOperand Reg:13>
35 ! CHECK-NEXT: <MCOperand Reg:14>
42 ! CHECK-NEXT: <MCOperand Reg:13>
43 ! CHECK-NEXT: <MCOperand Reg:14>
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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp62 .addReg(Reg) in loadImmediate()
98 if (PPC::GPRCRegClass.contains(Reg)) in setRegTo()
99 return {loadImmediate(Reg, 32, Value)}; in setRegTo()
100 if (PPC::G8RCRegClass.contains(Reg)) in setRegTo()
101 return {loadImmediate(Reg, 64, Value)}; in setRegTo()
102 if (PPC::F4RCRegClass.contains(Reg)) in setRegTo()
108 if (PPC::VRRCRegClass.contains(Reg)) in setRegTo()
111 if (PPC::VSRCRegClass.contains(Reg)) in setRegTo()
114 .addReg(Reg) in setRegTo()
117 if (PPC::VFRCRegClass.contains(Reg)) in setRegTo()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUResourceUsageAnalysis.cpp183 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
184 HighestVGPRReg = Reg; in analyzeResourceUsage()
192 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
193 HighestAGPRReg = Reg; in analyzeResourceUsage()
204 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
205 HighestSGPRReg = Reg; in analyzeResourceUsage()
238 Register Reg = MO.getReg(); in analyzeResourceUsage() local
239 switch (Reg) { in analyzeResourceUsage()
308 if (AMDGPU::SReg_32RegClass.contains(Reg) || in analyzeResourceUsage()
309 AMDGPU::SReg_LO16RegClass.contains(Reg) || in analyzeResourceUsage()
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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dmicromips-pseudo-mtlohi-expand.ll11 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
14 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
17 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
19 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
21 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
22 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
24 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
26 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
28 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
33 ; MMR2-DSP-NEXT: # <MCOperand Reg:{{[0-9]+}}>
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64TargetStreamer.h50 virtual void emitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveReg() argument
51 virtual void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegX() argument
52 virtual void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegP() argument
53 virtual void emitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegPX() argument
55 virtual void emitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFReg() argument
56 virtual void emitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegX() argument
57 virtual void emitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegP() argument
103 void emitARM64WinCFISaveReg(unsigned Reg, int Offset) override;
104 void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) override;
105 void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) override;
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
118 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
119 return Reg; in getDefReg()
124 return Reg; in getDefReg()
128 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
129 return Reg; in getDefReg()
132 return Reg; in getDefReg()
135 return Reg; in getDefReg()
165 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
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