Lines Matching refs:Reg
70 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
71 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
85 Regs.push_back(Reg); in GetGroupRegs()
104 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { in LeaveGroup() argument
110 GroupNodeIndices[Reg] = idx; in LeaveGroup()
114 bool AggressiveAntiDepState::IsLive(unsigned Reg) { in IsLive() argument
117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
158 unsigned Reg = *AI; in StartBlock() local
159 State->UnionGroups(Reg, 0); in StartBlock()
160 KillIndices[Reg] = BB->size(); in StartBlock()
161 DefIndices[Reg] = ~0u; in StartBlock()
172 unsigned Reg = *I; in StartBlock() local
173 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
175 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
203 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
210 if (State->IsLive(Reg)) { in Observe()
211 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() in Observe()
212 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
214 State->UnionGroups(Reg, 0); in Observe()
215 } else if ((DefIndices[Reg] < InsertPosIndex) in Observe()
216 && (DefIndices[Reg] >= Count)) { in Observe()
217 DefIndices[Reg] = Count; in Observe()
228 Register Reg = MO.getReg(); in IsImplicitDefUse() local
229 if (Reg == 0) in IsImplicitDefUse()
234 Op = MI.findRegisterUseOperand(Reg, true); in IsImplicitDefUse()
236 Op = MI.findRegisterDefOperand(Reg); in IsImplicitDefUse()
248 const Register Reg = MO.getReg(); in GetPassthruRegs() local
249 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs()
292 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, in HandleLastUse() argument
305 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in HandleLastUse()
306 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) { in HandleLastUse()
311 if (!State->IsLive(Reg)) { in HandleLastUse()
312 KillIndices[Reg] = KillIdx; in HandleLastUse()
313 DefIndices[Reg] = ~0u; in HandleLastUse()
314 RegRefs.erase(Reg); in HandleLastUse()
315 State->LeaveGroup(Reg); in HandleLastUse()
317 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
320 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag); in HandleLastUse()
325 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandleLastUse()
333 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
358 Register Reg = MO.getReg(); in PrescanInstruction() local
359 if (Reg == 0) continue; in PrescanInstruction()
361 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n"); in PrescanInstruction()
368 Register Reg = MO.getReg(); in PrescanInstruction() local
369 if (Reg == 0) continue; in PrescanInstruction()
371 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in PrescanInstruction()
372 << State->GetGroup(Reg)); in PrescanInstruction()
381 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); in PrescanInstruction()
382 State->UnionGroups(Reg, 0); in PrescanInstruction()
387 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { in PrescanInstruction()
390 State->UnionGroups(Reg, AliasReg); in PrescanInstruction()
391 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " in PrescanInstruction()
401 RegRefs.insert(std::make_pair(Reg, RR)); in PrescanInstruction()
410 Register Reg = MO.getReg(); in PrescanInstruction() local
411 if (Reg == 0) continue; in PrescanInstruction()
413 if (MI.isKill() || (PassthruRegs.count(Reg) != 0)) in PrescanInstruction()
417 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in PrescanInstruction()
424 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) in PrescanInstruction()
463 Register Reg = MO.getReg(); in ScanInstruction() local
464 if (Reg == 0) continue; in ScanInstruction()
466 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in ScanInstruction()
467 << State->GetGroup(Reg)); in ScanInstruction()
472 HandleLastUse(Reg, Count, "(last-use)"); in ScanInstruction()
475 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); in ScanInstruction()
476 State->UnionGroups(Reg, 0); in ScanInstruction()
484 RegRefs.insert(std::make_pair(Reg, RR)); in ScanInstruction()
497 Register Reg = MO.getReg(); in ScanInstruction() local
498 if (Reg == 0) continue; in ScanInstruction()
501 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); in ScanInstruction()
502 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
504 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in ScanInstruction()
505 FirstReg = Reg; in ScanInstruction()
513 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) { in GetRenameRegisters() argument
520 for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) { in GetRenameRegisters()
563 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters() local
564 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) in FindSuitableFreeRegisters()
565 SuperReg = Reg; in FindSuitableFreeRegisters()
568 if (RegRefs.count(Reg) > 0) { in FindSuitableFreeRegisters()
569 LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":"); in FindSuitableFreeRegisters()
571 BitVector &BV = RenameRegisterMap[Reg]; in FindSuitableFreeRegisters()
573 BV = GetRenameRegisters(Reg); in FindSuitableFreeRegisters()
585 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters() local
586 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
587 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
646 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters() local
648 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
651 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
659 if (!RenameRegisterMap[Reg].test(NewReg)) { in FindSuitableFreeRegisters()
668 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) { in FindSuitableFreeRegisters()
676 (KillIndices[Reg] > DefIndices[AliasReg])) { in FindSuitableFreeRegisters()
689 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) { in FindSuitableFreeRegisters()
704 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) { in FindSuitableFreeRegisters()
716 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg)); in FindSuitableFreeRegisters()
781 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { in BreakAntiDependencies() local
782 if (!State->IsLive(Reg)) in BreakAntiDependencies()
783 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in BreakAntiDependencies()