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Searched refs:RecVec (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp254 const RecVec Defs = in checkSTIPredicates()
603 RecVec SWDefs, SRDefs; in collectSchedRW()
751 RecVec &WriteDefs, RecVec &ReadDefs) { in splitSchedReadWrites()
765 RecVec WriteDefs; in findRWs()
766 RecVec ReadDefs; in findRWs()
1276 const RecVec *InstDefs = Sets.expand(Rec); in inferFromInstRWs()
1658 static void dumpRecVec(const RecVec &RV) { in dumpRecVec()
1704 RecVec Preds; in inferFromTransitions()
1816 RecVec CheckUnits = in verifyProcResourceGroups()
1821 RecVec OtherUnits = in verifyProcResourceGroups()
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H A DCodeGenSchedule.h29 using RecVec = std::vector<Record*>; variable
52 RecVec Aliases;
96 RecVec PredTerm;
139 RecVec InstRWs;
225 RecVec ItinDefList;
229 RecVec ItinRWDefs;
236 RecVec WriteResDefs;
237 RecVec ReadAdvanceDefs;
240 RecVec ProcResourceDefs;
435 RecVec ProcResourceDefs;
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H A DPredicateExpander.h55 using RecVec = std::vector<Record *>; variable
72 void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
73 void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
74 void expandPredicateSequence(raw_ostream &OS, const RecVec &Sequence,
89 void expandOpcodeSwitchStatement(raw_ostream &OS, const RecVec &Cases,
H A DPredicateExpander.cpp118 const RecVec &Opcodes) { in expandCheckOpcode()
148 const RecVec &Opcodes) { in expandCheckPseudo()
156 const RecVec &Sequence, in expandPredicateSequence()
241 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes"); in expandOpcodeSwitchCase()
255 const RecVec &Cases, in expandOpcodeSwitchStatement()
422 RecVec Delegates = Fn.getDeclaration()->getValueAsListOfDefs("Delegates"); in expandPrologue()
H A DSubtargetEmitter.cpp179 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList, in printFeatureMask()
268 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
335 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
348 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
394 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
426 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
440 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
666 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResourceSubUnits()
826 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); in EmitProcessorResources()
968 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec, in ExpandProcResources()
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H A DDFAPacketizerEmitter.cpp82 void createScheduleClasses(unsigned ItineraryIdx, const RecVec &Itineraries);
191 const RecVec &Itineraries) { in createScheduleClasses()
H A DInstrInfoEmitter.cpp673 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitMCIIHelperMethods()
860 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitTIIHelperMethods()
H A DRegisterInfoEmitter.cpp1594 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()
H A DCodeGenRegisters.cpp756 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
/llvm-project-15.0.7/llvm/include/llvm/TableGen/
H A DSetTheory.h66 using RecVec = std::vector<Record *>;
97 using ExpandMap = std::map<Record *, RecVec>;
139 const RecVec *expand(Record *Set);
/llvm-project-15.0.7/llvm/lib/TableGen/
H A DSetTheory.cpp35 using RecVec = SetTheory::RecVec; typedef
229 if (const RecVec *Result = ST.expand(Rec)) in apply()
284 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
307 const RecVec *SetTheory::expand(Record *Set) { in expand()
322 RecVec &EltVec = Expansions[Set]; in expand()