[CodeGen] Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added

[CodeGen] Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo. The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Recommitted with some fixes for the leftover MCII variables in release
builds.

Differential Revision: https://reviews.llvm.org/D129506

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Revert "Move instruction predicate verification to emitInstruction"

This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does
not build for Release builds, and some buildbots are givin

Revert "Move instruction predicate verification to emitInstruction"

This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does
not build for Release builds, and some buildbots are giving more warning
than I saw locally. Reverting to fix those issues.

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Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Targ

Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo. The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Differential Revision: https://reviews.llvm.org/D129506

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[TableGen] Add a knob for MCOperandInfo expansion in gen-instr-info

Control the MCOperandInfo expansion with `-instr-info-expand-mi-operand-info`.
For X86, this would make it possible to see memory

[TableGen] Add a knob for MCOperandInfo expansion in gen-instr-info

Control the MCOperandInfo expansion with `-instr-info-expand-mi-operand-info`.
For X86, this would make it possible to see memory operand type e.g.:
```
/* MOV8rm */
GR8, i8mem,
/* MOV8rm_NOREX */
GR8_NOREX, i8mem_NOREX,
```

The intended use is a follow-up diff D126116 (`getMemOperandSize`).

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D127932

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[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE

Make Offsets and OpcodeOperandTypes tables human-readable by printing the
instruction name before the operand list.

In effect, this makes

[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE

Make Offsets and OpcodeOperandTypes tables human-readable by printing the
instruction name before the operand list.

In effect, this makes debugging generated `getOperandType` possible.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D127931

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Revert "[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE"

This reverts commit 4cd416193cc126355a22b2c9e5c1df3a49b59e50.

[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE

Make Offsets and OpcodeOperandTypes tables human-readable by printing the
instruction name before the operand list.

In effect, this makes

[TableGen] Emit instruction name in INSTRINFO_OPERAND_TYPE

Make Offsets and OpcodeOperandTypes tables human-readable by printing the
instruction name before the operand list.

In effect, this makes debugging generated `getOperandType` possible.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D127931

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[TableGen][X86] Add Size field to X86MemOperand class

Set Size appropriately in operand definitions and query it for dumping memory
operand size table `getMemOperandSize` (follow-up use D126116) and

[TableGen][X86] Add Size field to X86MemOperand class

Set Size appropriately in operand definitions and query it for dumping memory
operand size table `getMemOperandSize` (follow-up use D126116) and
`X86Disassembler::getMemOperandSize`.

Excerpt from a produced `getMemOperandSize` table for X86:

```
static int getMemOperandSize(int OpType) {
switch (OpType) {
default: return 0;
case OpTypes::i8mem:
case OpTypes::i8mem_NOREX:
return 8;

case OpTypes::f16mem:
case OpTypes::i16mem:
return 16;

case OpTypes::f32mem:
case OpTypes::i32mem:
return 32;
...
```

Reviewed By: skan, pengfei

Differential Revision: https://reviews.llvm.org/D127787

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[Codegen][tablgen][NFC] Allow meta instruction to be target dependent

An instruction is a meta-instruction if it doesn't produce any output
in the form of executable instructions. So in the concept,

[Codegen][tablgen][NFC] Allow meta instruction to be target dependent

An instruction is a meta-instruction if it doesn't produce any output
in the form of executable instructions. So in the concept, a
meta-instruction does not have to be target independent.

Before this patch, `isMetaInstruction` is implemented by checking the
opcode of the instruction, add we have no way to add target dependent
opcode to the list, which does not make sense.

After this patch, a bit `isMeta` is added for class `Instruction` in
tablegen, which is used to indicate whether it's a meta instruction.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D121600

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[llvm] Fix bugprone argument comments (NFC)

Identified with bugprone-argument-comment.

[TableGen] Use range-based for loops (NFC)

Use range-based for loops in TableGen.

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D101994

[M68k][TableGen](1/8) TableGen related changes

- Add a new TableGen backend: CodeBeads
- Add support to generate logical operand information

For the first item, it is currently a workaround of M6

[M68k][TableGen](1/8) TableGen related changes

- Add a new TableGen backend: CodeBeads
- Add support to generate logical operand information

For the first item, it is currently a workaround of M68k's (complex)
instruction encoding. A typical architecture, especially CISC one like
X86, normally uses `MCInstrDesc::TSFlags` to carry instruction encoding
info. However, at the early days of M68k backend development, we found
it difficult to fit every possible encoding into the 64-bit
`MCInstrDesc::TSFlags`. Therefore CodeBeads was invented to provide
an alternative, arbitrary length container for instruciton encoding
info. However, in the long term we incline not to use a new TG
backend for less common pattern like what we encountered in M68k. A bug
has been created to host to discussion on migrating from CodeBeads to
more concise solution: https://bugs.llvm.org/show_bug.cgi?id=48792

The second item was also served for similar purpose. It created utility
functions that tell you the index of a `MachineOperand` in a
`MachineInst` given a logical operand index. In normal cases a logical
operand is the same as `MachineOperand`, but for operands using complex
addressing mode a logical operand might be consisting of multiple
`MachineOperand`. The TableGen-ed `getLogicalOperandIdx`, for instance,
can give you the mapping between these two concepts. Nevertheless, we
hope to remove this feature in the future if possible. Since it's not
really useful for the targets supported by LLVM now either.

Authors: myhsu, m4yers, glaubitz

Differential Revision: https://reviews.llvm.org/D88385

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[llvm] Drop unnecessary make_range (NFC)

[MCInstrDesc] [TableGen] Reduce size of MCOperandInfo instances.

Differential Revision: https://reviews.llvm.org/D93326

[TableGen] Slim down the data structures in xxxGenInstrInfo.inc, step 1

[TableGen] Cache the vectors of records returned by getAllDerivedDefinitions().

Differential Revision: https://reviews.llvm.org/D92674

[TableGen] Indentation and whitespace fixes in generated code. NFC.

Some of these were found by running clang-format over the generated
code, although that complains about far more issues than I hav

[TableGen] Indentation and whitespace fixes in generated code. NFC.

Some of these were found by running clang-format over the generated
code, although that complains about far more issues than I have fixed
here.

Differential Revision: https://reviews.llvm.org/D90937

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TableGen: Don't reconstruct CodeGenDAGTarget

This is quite expensive and it's already available.

Just ReadLegalValueTypes is taking 4 seconds for me in a debug build
for AMDGPU's -gen-instr-info, a

TableGen: Don't reconstruct CodeGenDAGTarget

This is quite expensive and it's already available.

Just ReadLegalValueTypes is taking 4 seconds for me in a debug build
for AMDGPU's -gen-instr-info, and this was introducing a second call.

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[MC] Move deprecation infos from MCTargetDesc to MCInstrInfo

This allows emitting it only when the feature is used by a target.
Shrinks Release+Asserts clang by 900k.

Make llvm::StringRef to std::string conversions explicit.

This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly m

Make llvm::StringRef to std::string conversions explicit.

This is how it should've been and brings it more in line with
std::string_view. There should be no functional change here.

This is mostly mechanical from a custom clang-tidy check, with a lot of
manual fixups. It uncovers a lot of minor inefficiencies.

This doesn't actually modify StringRef yet, I'll do that in a follow-up.

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[tablegen] Emit string literals instead of char arrays

This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this
form:
extern const char HexagonInstrNameData[] = {
/* 0 */ '

[tablegen] Emit string literals instead of char arrays

This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this
form:
extern const char HexagonInstrNameData[] = {
/* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
/* 9 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', '0', 0,
/* 18 */ 'V', '6', '_', 'v', 'd', 'd', '0', 0,
/* 26 */ 'P', 'S', '_', 'v', 'd', 'd', '0', 0,
[...]
};

...to this:

extern const char HexagonInstrNameData[] = {
/* 0 */ "G_FLOG10\0"
/* 9 */ "ENDLOOP0\0"
/* 18 */ "V6_vdd0\0"
/* 26 */ "PS_vdd0\0"
[...]
};

This should make debugging and exploration a lot easier for mortals,
while providing a significant compile-time reduction for common compilers.

To avoid issues with low implementation limits, this is disabled by
default for visual studio.

To force output one way or the other, pass
`--long-string-literals=<bool>` to `tablegen`

Reviewers: mstorsjo, rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D73044

A variation of this patch was originally committed in ce23515f5ab011 and
then reverted in e464b31c due to build failures.

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Revert "[tablegen] Emit string literals instead of char arrays"

This reverts commit ce23515f5ab01161c98449d833b3ae013b553aa8.

That commit broke some builds on Windows:
http://lab.llvm.org:8011/buil

Revert "[tablegen] Emit string literals instead of char arrays"

This reverts commit ce23515f5ab01161c98449d833b3ae013b553aa8.

That commit broke some builds on Windows:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/13870

show more ...

[tablegen] Emit string literals instead of char arrays

This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this
form:
extern const char HexagonInstrNameData[] = {
/* 0 */ '

[tablegen] Emit string literals instead of char arrays

This changes the generated (Instr|Asm|Reg|Regclass)Name tables from this
form:
extern const char HexagonInstrNameData[] = {
/* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
/* 9 */ 'E', 'N', 'D', 'L', 'O', 'O', 'P', '0', 0,
/* 18 */ 'V', '6', '_', 'v', 'd', 'd', '0', 0,
/* 26 */ 'P', 'S', '_', 'v', 'd', 'd', '0', 0,
[...]
};

...to this:

extern const char HexagonInstrNameData[] = {
/* 0 */ "G_FLOG10\0"
/* 9 */ "ENDLOOP0\0"
/* 18 */ "V6_vdd0\0"
/* 26 */ "PS_vdd0\0"
[...]
};

This should make debugging and exploration a lot easier for mortals,
while providing a significant compile-time reduction for common compilers.

To avoid issues with low implementation limits, this is disabled by
default for visual studio or when cross-compiling.

To force output one way or the other, pass
`--long-string-literals=<bool>` to `tablegen`

Reviewers: mstorsjo, rnk

Subscribers: llvm-commit

Differential Revision: https://reviews.llvm.org/D73044

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[AArch64] Add isAuthenticated predicate to MCInstDesc

Add a predicate to MCInstDesc that allows tools to determine whether an
instruction authenticates a pointer. This can be used by diagnostic
tool

[AArch64] Add isAuthenticated predicate to MCInstDesc

Add a predicate to MCInstDesc that allows tools to determine whether an
instruction authenticates a pointer. This can be used by diagnostic
tools to hint at pointer authentication failures.

Differential Revision: https://reviews.llvm.org/D70329

rdar://55089604

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[ms] [X86] Use "P" modifier on all branch-target operands in inline X86 assembly.

Summary:
Extend D71677 to apply to all branch-target operands, rather than special-casing call instructions.

Also a

[ms] [X86] Use "P" modifier on all branch-target operands in inline X86 assembly.

Summary:
Extend D71677 to apply to all branch-target operands, rather than special-casing call instructions.

Also add a regression test for llvm.org/PR44272, since this finishes fixing it.

Reviewers: thakis, rnk

Reviewed By: thakis

Subscribers: merge_guards_bot, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D72417

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