240   const RecVec Decls = Records.getAllDerivedDefinitions("STIPredicateDecl");  in checkSTIPredicates()
254   const RecVec Defs =  in checkSTIPredicates()
257     RecVec Opcodes = R->getValueAsListOfDefs("Opcodes");  in checkSTIPredicates()
298     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
304       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
329     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
336       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
403   RecVec RV = Records.getAllDerivedDefinitions("STIPredicate");  in collectSTIPredicates()
439   RecVec MCPredicates = Records.getAllDerivedDefinitions("TIIPredicate");  in checkMCInstPredicates()
461   RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit");  in collectRetireControlUnits()
476   RecVec Queues = Records.getAllDerivedDefinitions("MemoryQueue");  in collectLoadStoreQueueInfo()
520   RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");  in collectProcModels()
570 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,  in scanSchedRW()
577     RecVec Seq = RWDef->getValueAsListOfDefs("Writes");  in scanSchedRW()
583     RecVec Vars = RWDef->getValueAsListOfDefs("Variants");  in scanSchedRW()
586       RecVec Selected = Variant->getValueAsListOfDefs("Selected");  in scanSchedRW()
603   RecVec SWDefs, SRDefs;  in collectSchedRW()
608     RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");  in collectSchedRW()
619   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedRW()
622     RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
633   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectSchedRW()
636     RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
648   RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");  in collectSchedRW()
705       } RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");  in collectSchedRW()
742     RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");  in hasReadOfWrite()
750 static void splitSchedReadWrites(const RecVec &RWDefs,  in splitSchedReadWrites()
751                                  RecVec &WriteDefs, RecVec &ReadDefs) {  in splitSchedReadWrites()
763 void CodeGenSchedModels::findRWs(const RecVec &RWDefs,  in findRWs()
765   RecVec WriteDefs;  in findRWs()
766   RecVec ReadDefs;  in findRWs()
773 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,  in findRWs()
891   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedClasses()
939     const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;  in collectSchedClasses()
997 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {  in createSchedClassName()
1054   const RecVec *InstDefs = Sets.expand(InstRWDef);  in createInstRWClass()
1073       const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;  in createInstRWClass()
1075         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);  in createInstRWClass()
1161     RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");  in collectProcItins()
1201   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectProcItinRW()
1256       RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");  in inferFromItinClass()
1276     const RecVec *InstDefs = Sets.expand(Rec);  in inferFromInstRWs()
1380     RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in mutuallyExclusive()
1446       const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1478       const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1528     RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");  in pushVariant()
1658 static void dumpRecVec(const RecVec &RV) {  in dumpRecVec()
1667                            const RecVec &Preds) {  in dumpTransition()
1704     RecVec Preds;  in inferFromTransitions()
1794 bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {  in hasSuperGroup()
1798     RecVec SuperUnits = ProcResourceDef->getValueAsListOfDefs("Resources");  in hasSuperGroup()
1816     RecVec CheckUnits =  in verifyProcResourceGroups()
1821       RecVec OtherUnits =  in verifyProcResourceGroups()
1841   RecVec RegisterFileDefs = Records.getAllDerivedDefinitions("RegisterFile");  in collectRegisterFiles()
1863     RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");  in collectRegisterFiles()
1908   RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");  in collectProcResources()
1913   RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");  in collectProcResources()
1918   RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");  in collectProcResources()
1923   RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");  in collectProcResources()
1932   RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");  in collectProcResources()
2012       const RecVec &InstRWs = SC.InstRWs;  in checkCompleteness()
2045       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");  in collectItinProcResources()
2169   RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;  in addWriteRes()
2175   RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");  in addWriteRes()
2184   RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;  in addReadAdvance()