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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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| #
fbbc41f8 |
| 09-Mar-2022 |
serge-sans-paille <[email protected]> |
Cleanup include: TableGen
This also includes a few cleanup from Support.
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.l
Cleanup include: TableGen
This also includes a few cleanup from Support.
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121331
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Revision tags: llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init |
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| #
16978d85 |
| 01-Feb-2022 |
Jonas Paulsson <[email protected]> |
[TableGen] Fix reporting from CodeGenSchedModels::checkCompleteness().
Make the check for a complete SchedModel work as expected: report any
supported instruction not having scheduler info.
For unc
[TableGen] Fix reporting from CodeGenSchedModels::checkCompleteness().
Make the check for a complete SchedModel work as expected: report any
supported instruction not having scheduler info.
For unclear reasons there was a variable 'HadCompleteModel' that caused
e.g. new instructions for a new subtarget not to be reported. This variable
is now simply removed as all in-tree targets seem to build fine without it.
Review: Simon Pilgrim
Differential Revision: https://reviews.llvm.org/D118628
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| #
1aeb3314 |
| 29-Jan-2022 |
Craig Topper <[email protected]> |
[TableGen] Detect multiple Processors with the same name.
Due to a bad merge we ended up with duplicate entries in our
downstream repo. I was surprised that nothing caught it. I wrote
this check so
[TableGen] Detect multiple Processors with the same name.
Due to a bad merge we ended up with duplicate entries in our
downstream repo. I was surprised that nothing caught it. I wrote
this check so I could fix our downstream repo and figured I might
as well share it.
Reviewed By: RKSimon, spatel
Differential Revision: https://reviews.llvm.org/D118497
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Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
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| #
36b8a4f9 |
| 11-Dec-2021 |
Kazu Hirata <[email protected]> |
[llvm] Use llvm::is_contained (NFC)
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Revision tags: llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1 |
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| #
e6cf3d64 |
| 06-May-2021 |
Coelacanthus <[email protected]> |
[TableGen] Use range-based for loops (NFC)
Use range-based for loops in TableGen.
Reviewed By: Paul-C-Anagnostopoulos
Differential Revision: https://reviews.llvm.org/D101994
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Revision tags: llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2 |
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| #
b16c6b2a |
| 11-Feb-2021 |
Kazu Hirata <[email protected]> |
[TableGen] Use ListSeparator (NFC)
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| #
643c00f7 |
| 04-Feb-2021 |
Kazu Hirata <[email protected]> |
[TableGen] Use ListSeparator (NFC)
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Revision tags: llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init |
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| #
5d3f3d3a |
| 26-Jan-2021 |
Kazu Hirata <[email protected]> |
[TableGen] Use llvm::append_range (NFC)
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Revision tags: llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1 |
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| #
6a6e3821 |
| 09-Jan-2021 |
Kazu Hirata <[email protected]> |
[llvm] Drop unnecessary make_range (NFC)
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| #
f7f42e64 |
| 02-Jan-2021 |
Kazu Hirata <[email protected]> |
[TableGen] Use llvm::append_range (NFC)
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| #
9c978dd6 |
| 18-Dec-2020 |
Fangrui Song <[email protected]> |
[TableGen] Fix D90844 introduced non-determinism due to iteration over a std::map over allocated object pointers
993eaf2d69d8beb97e4695cbd919b927ed1cfe86 (D90844) is still wrong.
The allocated const
[TableGen] Fix D90844 introduced non-determinism due to iteration over a std::map over allocated object pointers
993eaf2d69d8beb97e4695cbd919b927ed1cfe86 (D90844) is still wrong.
The allocated const Record* pointers do not have an order guarantee
so switching from DenseMap to std::map does not help.
ProcModelMapTy = std::map<const Record*, unsigned>
Sort the values instead.
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Revision tags: llvmorg-11.0.1, llvmorg-11.0.1-rc2 |
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| #
e4a23a41 |
| 10-Dec-2020 |
Kazu Hirata <[email protected]> |
[Tablegen] Use llvm::is_contained (NFC)
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| #
53401e8e |
| 07-Dec-2020 |
Evgeny Leviant <[email protected]> |
[TableGen][SchedModels] Simplify the code. NFC
Differential revision: https://reviews.llvm.org/D92304
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| #
993eaf2d |
| 04-Dec-2020 |
Evgeny Leviant <[email protected]> |
Recommit [TableGen][SchedModels] Fix read/write variant substitution
Original commit rG112b3cb6ba49 introduced non-determinism in subtarget
generator due to iteration over DenseMap. New patch fixes
Recommit [TableGen][SchedModels] Fix read/write variant substitution
Original commit rG112b3cb6ba49 introduced non-determinism in subtarget
generator due to iteration over DenseMap. New patch fixes this changing
ProcModelMapTy from DenseMap to std::map.
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| #
86fa8963 |
| 03-Dec-2020 |
Fangrui Song <[email protected]> |
Revert D90844 "[TableGen][SchedModels] Fix read/write variant substitution"
This reverts commit 112b3cb6ba49aacd821440d0913f15b32131480e.
D90844 made lib/Target/AArch64/AArch64GenSubtargetInfo.inc
Revert D90844 "[TableGen][SchedModels] Fix read/write variant substitution"
This reverts commit 112b3cb6ba49aacd821440d0913f15b32131480e.
D90844 made lib/Target/AArch64/AArch64GenSubtargetInfo.inc non-deterministic.
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| #
112b3cb6 |
| 30-Nov-2020 |
Evgeny Leviant <[email protected]> |
[TableGen][SchedModels] Fix read/write variant substitution
Patch fixes multiple issues related to expansion of variant sched reads and
writes.
Differential revision: https://reviews.llvm.org/D90844
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| #
4c419c45 |
| 27-Nov-2020 |
Evgeny Leviant <[email protected]> |
[TableGen][SchedModels] Get rid of hasVariant. NFC
Differential revision: https://reviews.llvm.org/D92026
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Revision tags: llvmorg-11.0.1-rc1 |
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| #
d8f22c77 |
| 25-Nov-2020 |
Evgeny Leviant <[email protected]> |
[SchedModels] Return earlier removed checks
It is possible that some write resource is variant in model A
and sequence in model B. Such case will trigger assertion in
getAllPredicates function.
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| #
a2b59048 |
| 24-Nov-2020 |
Evgeny Leviant <[email protected]> |
[SchedModels] Improve diagnostics. NFC
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| #
78caf4f1 |
| 24-Nov-2020 |
Evgeny Leviant <[email protected]> |
[SchedModels] Limit set of predicates seen by mutuallyExclusive
Patch limits set of predicates seen by mutuallyExclusive to ones which belong
to current processor model. This needs to be done, becau
[SchedModels] Limit set of predicates seen by mutuallyExclusive
Patch limits set of predicates seen by mutuallyExclusive to ones which belong
to current processor model. This needs to be done, because same predicate can
be used by multiple processor models which can make mutuallyExclusive over
optimistic.
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| #
50bd6866 |
| 24-Nov-2020 |
Evgeny Leviant <[email protected]> |
Add support for branch forms of ALU instructions to Cortex-A57 model
Patch fixes scheduling of ALU instructions which modify pc register. Patch
also fixes computation of mutually exclusive predicate
Add support for branch forms of ALU instructions to Cortex-A57 model
Patch fixes scheduling of ALU instructions which modify pc register. Patch
also fixes computation of mutually exclusive predicates for sequences of
variants to be properly expanded
Differential revision: https://reviews.llvm.org/D91266
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| #
5abf76fb |
| 13-Nov-2020 |
Duncan P. N. Exon Smith <[email protected]> |
ADT: Add assertions to SmallVector::insert, etc., for reference invalidation
2c196bbc6bd897b3dcc1d87a3baac28e1e88df41 asserted that
`SmallVector::push_back` doesn't invalidate the parameter when it
ADT: Add assertions to SmallVector::insert, etc., for reference invalidation
2c196bbc6bd897b3dcc1d87a3baac28e1e88df41 asserted that
`SmallVector::push_back` doesn't invalidate the parameter when it needs
to grow. Do the same for `resize`, `append`, `assign`, `insert`, and
`emplace_back`.
Differential Revision: https://reviews.llvm.org/D91744
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| #
cc96a822 |
| 02-Nov-2020 |
Evgeny Leviant <[email protected]> |
[TableGen][SchedModels] Fix read/write variant substitution
Patch fixes case when sched class has write and read variants belonging
to different processor models.
Differential revision: https://rev
[TableGen][SchedModels] Fix read/write variant substitution
Patch fixes case when sched class has write and read variants belonging
to different processor models.
Differential revision: https://reviews.llvm.org/D89777
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| #
836d0add |
| 13-Oct-2020 |
Evgeny Leviant <[email protected]> |
Fix Windows/MSVC build after 6e56046f65
Commit 6e56046f65 may trigger SEGV in llvm-tablegen if the latter
is built with -DLLVM_OPTIMIZED_TABLEGEN=OFF. The reason of SEGV was
accessing stale memory a
Fix Windows/MSVC build after 6e56046f65
Commit 6e56046f65 may trigger SEGV in llvm-tablegen if the latter
is built with -DLLVM_OPTIMIZED_TABLEGEN=OFF. The reason of SEGV was
accessing stale memory after expansion of std::vector.
show more ...
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| #
6e56046f |
| 13-Oct-2020 |
Evgeny Leviant <[email protected]> |
[TableGen][SchedModels] Fix aliasing of SchedWriteVariant
Differential revision: https://reviews.llvm.org/D89114
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