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Searched refs:RVLocs (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp282 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
403 return lowerCallResult(Chain, Glue, RVLocs, dl, DAG, InVals); in LowerCall()
414 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in lowerCallResult()
415 const CCValAssign &VA = RVLocs[i]; in lowerCallResult()
635 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
636 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
655 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
671 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
672 CCValAssign &VA = RVLocs[i]; in LowerReturn()
699 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp561 SmallVectorImpl<CCValAssign> &RVLocs, in AnalyzeReturnValues() argument
729 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
730 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
744 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
755 AnalyzeReturnValues(CCInfo, RVLocs, Outs); in LowerReturn()
761 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
762 CCValAssign &VA = RVLocs[i]; in LowerReturn()
941 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
945 AnalyzeReturnValues(CCInfo, RVLocs, Ins); in LowerCallResult()
948 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp509 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
513 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
527 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
528 CCValAssign &VA = RVLocs[i]; in LowerReturn()
555 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
556 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCallResult()
568 for (auto &Val : RVLocs) { in LowerCallResult()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp532 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
533 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
545 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
548 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
558 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
559 CCValAssign &VA = RVLocs[i]; in LowerReturn()
784 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
785 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
791 for (unsigned I = 0; I != RVLocs.size(); ++I) { in LowerCallResult()
792 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp235 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
261 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_32() local
277 i != RVLocs.size(); in LowerReturn_32()
279 CCValAssign &VA = RVLocs[i]; in LowerReturn_32()
344 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_64() local
362 CCValAssign &VA = RVLocs[i]; in LowerReturn_64()
390 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
1073 SmallVector<CCValAssign, 16> RVLocs; in LowerCall_32() local
1082 if (RVLocs[i].getLocVT() == MVT::v2i32) { in LowerCall_32()
1383 SmallVector<CCValAssign, 16> RVLocs; in LowerCall_64() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp2032 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
2037 if (RVLocs.size() == 2 && RetVT == MVT::f64) { in FinishCall()
2040 MVT DestVT = RVLocs[0].getValVT(); in FinishCall()
2048 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2049 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2055 MVT CopyVT = RVLocs[0].getValVT(); in FinishCall()
2067 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2215 SmallVector<CCValAssign, 16> RVLocs; in ARMEmitLibcall() local
2218 if (RVLocs.size() >= 2 && RetVT != MVT::f64) in ARMEmitLibcall()
2324 SmallVector<CCValAssign, 16> RVLocs; in SelectCall() local
[all …]
H A DARMISelLowering.cpp2173 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2179 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2180 CCValAssign VA = RVLocs[i]; in LowerCallResult()
2199 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
2213 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
3098 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3143 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
3159 AFI->setReturnRegsCount(RVLocs.size()); in LowerReturn()
3174 i != RVLocs.size(); in LowerReturn()
3176 CCValAssign &VA = RVLocs[i]; in LowerReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1064 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
1065 const CCValAssign &VA = RVLocs[i]; in LowerCallResult()
1122 SmallVector<CCValAssign, 16> RVLocs; in LowerCCCCallTo() local
1226 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); in LowerCCCCallTo()
1424 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1425 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
1446 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1466 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
1467 CCValAssign &VA = RVLocs[i]; in LowerReturn()
1494 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1025 SmallVector<CCValAssign> RVLocs; in LowerCall() local
1026 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCall()
1030 for (auto &VA : RVLocs) { in LowerCall()
1057 SmallVector<CCValAssign> RVLocs; in LowerReturn() local
1060 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
1069 for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) { in LowerReturn()
1070 CCValAssign &VA = RVLocs[i]; in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1491 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1492 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
1503 for (CCValAssign const &RVLoc : RVLocs) { in LowerCallResult()
1522 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1523 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
1538 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1541 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
1556 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
1557 CCValAssign &VA = RVLocs[i]; in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp71 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
72 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
362 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
365 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
375 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
376 CCValAssign &VA = RVLocs[i]; in LowerReturn()
779 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
780 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCall()
791 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCall()
792 CCValAssign &VA = RVLocs[i]; in LowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1502 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1503 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1505 CCValAssign &VA = RVLocs[0]; in finishCall()
1506 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); in finishCall()
1588 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
1589 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context); in fastLowerCall()
1591 if (RVLocs.size() > 1) in fastLowerCall()
H A DPPCISelLowering.cpp5135 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
5136 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
5145 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
5146 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
5156 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
7541 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
7542 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
7555 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
7556 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
7568 CCValAssign &VA = RVLocs[i]; in LowerReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1275 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1276 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1283 if (RVLocs.size() != 1) in finishCall()
1286 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
1296 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1297 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
H A DMipsISelLowering.cpp3503 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
3513 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
3514 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
3517 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3518 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
3795 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3796 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
3828 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
3832 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
3841 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp189 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
190 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
207 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
210 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
223 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
224 CCValAssign &VA = RVLocs[i]; in LowerReturn()
355 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
366 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
368 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
389 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp842 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
843 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
848 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
849 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
1023 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1024 CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
1036 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerReturn()
1037 CCValAssign &VA = RVLocs[i]; in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp3525 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
3526 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, in fastLowerCall()
3532 for (unsigned i = 0; i != RVLocs.size(); ++i) { in fastLowerCall()
3533 CCValAssign &VA = RVLocs[i]; in fastLowerCall()
3575 CLI.NumResultRegs = RVLocs.size(); in fastLowerCall()
H A DX86ISelLowering.cpp3014 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3015 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
3100 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
3107 CCValAssign &VA = RVLocs[I]; in LowerReturn()
3444 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
3450 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E; in LowerCallResult()
3452 CCValAssign &VA = RVLocs[I]; in LowerCallResult()
5130 SmallVector<CCValAssign, 16> RVLocs; in IsEligibleForTailCallOptimization() local
5131 CCState CCInfo(CalleeCC, false, MF, RVLocs, C); in IsEligibleForTailCallOptimization()
5133 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in IsEligibleForTailCallOptimization()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3092 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
3093 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
3097 if (RVLocs.size() != 1) in finishCall()
3101 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
3110 .addReg(RVLocs[0].getLocReg()); in finishCall()
3111 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
H A DAArch64ISelLowering.h897 const SmallVectorImpl<CCValAssign> &RVLocs,
H A DAArch64ISelLowering.cpp6160 const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &DL, in LowerCallResult() argument
6165 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
6166 CCValAssign VA = RVLocs[i]; in LowerCallResult()
6522 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
6536 if (any_of(RVLocs, HasSVERegLoc) || any_of(ArgLocs, HasSVERegLoc)) in LowerCall()
6972 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
6973 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
6987 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
6988 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
6995 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size(); in LowerReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp11424 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
11425 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCall()
11429 for (auto &VA : RVLocs) { in LowerCall()
11458 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
11459 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
11487 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
11490 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
11496 if (CallConv == CallingConv::GHC && !RVLocs.empty()) in LowerReturn()
11503 for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) { in LowerReturn()
11505 CCValAssign &VA = RVLocs[i]; in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp2593 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
2594 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
2618 SmallVector<CCValAssign, 48> RVLocs; in LowerReturn() local
2622 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
2633 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E; in LowerReturn()
2635 CCValAssign &VA = RVLocs[I]; in LowerReturn()
2701 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2702 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2707 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2708 CCValAssign VA = RVLocs[i]; in LowerCallResult()