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Searched refs:RR (Results 1 – 25 of 62) sorted by relevance

123

/llvm-project-15.0.7/polly/lib/Analysis/
H A DScopDetectionDiagnostic.cpp144 for (RejectReasonPtr RR : Log) { in emitRejectionRemarks() local
146 if (const DebugLoc &Loc = RR->getDebugLoc()) in emitRejectionRemarks()
149 << RR->getEndUserMessage()); in emitRejectionRemarks()
153 << RR->getEndUserMessage()); in emitRejectionRemarks()
193 bool ReportCFG::classof(const RejectReason *RR) { in classof() argument
194 return RR->getKind() >= RejectReasonKind::CFG && in classof()
195 RR->getKind() <= RejectReasonKind::LastCFG; in classof()
691 bool ReportAlias::classof(const RejectReason *RR) { in classof() argument
692 return RR->getKind() == RejectReasonKind::Alias; in classof()
704 bool ReportOther::classof(const RejectReason *RR) { in classof() argument
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRDFRegisters.cpp170 bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); in aliasRM()
174 if (RR.Mask == LaneBitmask::getAll()) in aliasRM()
185 LaneBitmask M = RR.Mask; in aliasRM()
188 if ((SM & RR.Mask).none()) in aliasRM()
231 if (RR.Reg == R) in mapTo()
232 return RR; in mapTo()
246 if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) in hasAliasOf()
260 BitVector T(PRI.getMaskUnits(RR.Reg)); in hasCoverOf()
275 Units |= PRI.getMaskUnits(RR.Reg); in insert()
302 return clear(RegisterAggr(PRI).insert(RR)); in clear()
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H A DRDFGraph.cpp419 Ref.PR = G.pack(RR); in setRegRef()
907 RegisterRef RR = *I; in build() local
1041 DefM[RR.Reg].push(DA); in pushClobbers()
1042 Defined.insert(RR.Reg); in pushClobbers()
1045 assert(A != RR.Reg); in pushClobbers()
1097 DefM[RR.Reg].push(DA); in pushDefs()
1100 assert(A != RR.Reg); in pushDefs()
1420 if (I != RR && RegisterAggr::isCoverOf(I, RR, PRI)) in buildPhis()
1421 RR = I; in buildPhis()
1422 return RR; in buildPhis()
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H A DRegisterClassInfo.cpp87 const BitVector &RR = MF->getRegInfo().getReservedRegs(); in runOnMachineFunction() local
88 if (Reserved.size() != RR.size() || RR != Reserved) { in runOnMachineFunction()
90 Reserved = RR; in runOnMachineFunction()
H A DRDFLiveness.cpp147 RegisterRef RR = TA.Addr->getRegRef(DFG); in getAllReachingDefs() local
149 if (RegisterAggr::isCoverOf(RR, RefRR, PRI)) in getAllReachingDefs()
658 auto ClearIn = [] (RegisterRef RR, const RegisterAggr &Mid, SubMap &SM) { in computePhiInfo() argument
660 return RR; in computePhiInfo()
661 auto F = SM.find(RR); in computePhiInfo()
664 RegisterRef S = Mid.clearIn(RR); in computePhiInfo()
665 SM.insert({RR, S}); in computePhiInfo()
727 RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(DFG); in computePhiInfo() local
728 dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>'; in computePhiInfo()
1128 RegisterRef RR = UA.Addr->getRegRef(DFG); in traverse() local
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/llvm-project-15.0.7/llvm/test/CodeGen/AVR/atomics/
H A Dload16.ll7 ; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD]]+1
36 ; CHECK-NEXT: st [[RR]], [[RR1L]]
37 ; CHECK-NEXT: std [[RR]]+1, [[RR1H]]
52 ; CHECK-NEXT: st [[RR]], [[TMPL]]
53 ; CHECK-NEXT: std [[RR]]+1, [[TMPH]]
67 ; CHECK-NEXT: st [[RR]], [[RD1L]]
68 ; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
82 ; CHECK-NEXT: st [[RR]], [[RD1L]]
83 ; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
97 ; CHECK-NEXT: st [[RR]], [[RD1L]]
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H A Dload8.ll8 ; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
33 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
35 ; CHECK-NEXT: st [[RR]], [[RR1]]
45 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
48 ; CHECK-NEXT: st [[RR]], [[TMP]]
58 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
60 ; CHECK-NEXT: st [[RR]], [[RR1]]
70 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
72 ; CHECK-NEXT: st [[RR]], [[RR1]]
82 ; CHECK-NEXT: ld [[RD:r[0-9]+]], [[RR:(X|Y|Z)]]
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H A Dstore.ll6 ; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
16 ; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
17 ; CHECK-NEXT: std [[RD]]+1, [[RR:r[0-9]+]]
H A Dstore16.ll6 ; CHECK-NEXT: st [[RD:(X|Y|Z)]], [[RR:r[0-9]+]]
7 ; CHECK-NEXT: std [[RD:(X|Y|Z)]]+1, [[RR:r[0-9]+]]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h83 bool operator== (const RegisterRef &RR) const {
84 return Reg == RR.Reg && Mask == RR.Mask;
88 return !operator==(RR);
91 bool operator< (const RegisterRef &RR) const {
92 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
175 bool hasAliasOf(RegisterRef RR) const;
176 bool hasCoverOf(RegisterRef RR) const;
187 RegisterAggr &insert(RegisterRef RR);
189 RegisterAggr &intersect(RegisterRef RR);
191 RegisterAggr &clear(RegisterRef RR);
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H A DRDFGraph.h525 void setRegRef(RegisterRef RR, DataFlowGraph &G);
553 NodeAddr<RefNode*> getNextRef(RegisterRef RR, Predicate P, bool NextOnly,
740 PackedRegisterRef pack(RegisterRef RR) { in pack()
741 return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) }; in pack()
743 PackedRegisterRef pack(RegisterRef RR) const { in pack()
744 return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) }; in pack()
822 RegisterRef RR, NodeAddr<BlockNode*> PredB,
827 RegisterRef RR, uint16_t Flags = NodeAttrs::PhiRef);
882 NodeAddr<RefNode*> RefNode::getNextRef(RegisterRef RR, Predicate P, in getNextRef() argument
891 if (RA.Addr->getRegRef(G) == RR && P(NA)) in getNextRef()
/llvm-project-15.0.7/polly/include/polly/
H A DScopDetectionDiagnostic.h201 static bool classof(const RejectReason *RR);
216 static bool classof(const RejectReason *RR);
240 static bool classof(const RejectReason *RR);
266 static bool classof(const RejectReason *RR);
292 static bool classof(const RejectReason *RR);
320 static bool classof(const RejectReason *RR);
341 static bool classof(const RejectReason *RR);
366 static bool classof(const RejectReason *RR);
389 static bool classof(const RejectReason *RR);
423 static bool classof(const RejectReason *RR);
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/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DResourceManager.cpp198 RS.markSubResourceAsUsed(RR.second); in use()
202 Strategies[RSID]->used(RR.second); in use()
209 AvailableProcResUnits ^= RR.first; in use()
218 Strategies[GroupIndex]->used(RR.first); in use()
228 RS.releaseSubResource(RR.second); in release()
232 AvailableProcResUnits ^= RR.first; in release()
339 const ResourceRef &RR = BR.first; in cycleEvent() local
341 if (countPopulation(RR.first) == 1) in cycleEvent()
342 release(RR); in cycleEvent()
343 releaseResource(RR.first); in cycleEvent()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp184 return Reg == RR.Reg && Sub == RR.Sub; in operator ==()
186 bool operator!= (RegisterRef RR) const { return !operator==(RR); } in operator !=()
188 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); in operator <()
769 RegisterRef RR = Op; in getReachingDefForPred() local
770 if (RR.Reg == PredR) { in getReachingDefForPred()
774 if (RR.Reg != RD.Reg) in getReachingDefForPred()
779 if (RR.Sub == RD.Sub) in getReachingDefForPred()
803 RegisterRef RR = Op; in canMoveOver() local
1003 RegisterRef RR = Op; in predicate() local
1013 RR.Sub = 0; in predicate()
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H A DBitTracker.cpp338 if (RR.Reg.isVirtual()) { in getRegBitWidth()
339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub); in getRegBitWidth()
342 assert(RR.Reg.isPhysical()); in getRegBitWidth()
344 (RR.Sub == 0) ? RR.Reg.asMCReg() : TRI.getSubReg(RR.Reg, RR.Sub); in getRegBitWidth()
354 if (RR.Reg.isPhysical()) in getCell()
357 assert(RR.Reg.isVirtual()); in getCell()
366 if (!RR.Sub) in getCell()
368 BitMask M = mask(RR.Reg, RR.Sub); in getCell()
380 if (!RR.Reg.isVirtual()) in putCell()
384 M[RR.Reg] = RC.regify(RR.Reg); in putCell()
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H A DRDFCopy.cpp121 auto MinPhysReg = [this] (RegisterRef RR) -> unsigned { in run() argument
123 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); in run()
124 if ((RC.LaneMask & RR.Mask) == RC.LaneMask) in run()
125 return RR.Reg; in run()
126 for (MCSubRegIndexIterator S(RR.Reg, &TRI); S.isValid(); ++S) in run()
127 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex())) in run()
H A DBitTracker.h53 RegisterCell get(RegisterRef RR) const;
54 void put(RegisterRef RR, const RegisterCell &RC);
397 uint16_t getRegBitWidth(const RegisterRef &RR) const;
399 RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
400 void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
405 RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const { in getRef()
406 RegisterCell RC = getCell(RR, M); in getRef()
H A DHexagonOptAddrMode.cpp172 RegisterRef RR = UA.Addr->getRegRef(*DFG); in canRemoveAddasl() local
173 if (OffsetReg == RR.Reg) { in canRemoveAddasl()
174 OffsetRR = RR; in canRemoveAddasl()
294 RegisterRef RR = UA.Addr->getRegRef(*DFG); in isSafeToExtLR() local
295 if (LRExtReg == RR.Reg) { in isSafeToExtLR()
296 LRExtRR = RR; in isSafeToExtLR()
458 RegisterRef RR = UA.Addr->getRegRef(*DFG); in processAddUses() local
459 if (BaseReg == RR.Reg) in processAddUses()
/llvm-project-15.0.7/clang/test/PCH/
H A Dcxx-reference.h4 typedef char (&&RR);
12 RR &lrrr = c;
13 RR &&rrrr = 'c';
/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/
H A DPointerSubChecker.cpp45 const MemRegion *RR = RV.getAsRegion(); in checkPreStmt() local
47 if (!(LR && RR)) in checkPreStmt()
51 const MemRegion *BaseRR = RR->getBaseRegion(); in checkPreStmt()
/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DExecuteStage.cpp103 for (const ResourceRef &RR : Freed) in cycleStart() local
104 notifyResourceAvailable(RR); in cycleStart()
245 void ExecuteStage::notifyResourceAvailable(const ResourceRef &RR) const { in notifyResourceAvailable()
246 LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.' in notifyResourceAvailable()
247 << RR.second << "]\n"); in notifyResourceAvailable()
249 Listener->onResourceAvailable(RR); in notifyResourceAvailable()
/llvm-project-15.0.7/llvm/test/Transforms/SROA/
H A Dpr37267.ll22 ; slice 3: RR
23 ; slice 4: RR
63 ; slice 3: RR
64 ; slice 4: RR
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DResourcePressureView.cpp59 const ResourceRef &RR = Use.first; in onEvent() local
60 assert(Resource2VecIndex.find(RR.first) != Resource2VecIndex.end()); in onEvent()
61 unsigned R2VIndex = Resource2VecIndex[RR.first]; in onEvent()
62 R2VIndex += countTrailingZeros(RR.second); in onEvent()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.td531 // Multiclass for generic RR type instructions
587 // Generic RR multiclass with 2 arguments.
668 // Generic RR multiclass with an argument.
681 // Special RR multiclass for MRG instruction.
722 def ir : RR<opc, (outs I64:$sx),
726 def rm : RR<opc, (outs I64:$sx),
730 def im : RR<opc, (outs I64:$sx),
1168 def SVOB : RR<0x30, (outs), (ins), "svob">;
1530 def NOP : RR<0x79, (outs), (ins), "nop">;
1948 RR CmpOpNode1,
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/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dfusion-push-reshape.mlir12 // CHECK: %[[RR:.*]] = tensor.expand_shape %[[R]] {{\[}}[0, 1], [2]] : tensor<?x16xf32> into t…
13 // CHECK: return %[[RR]] : tensor<?x112x16xf32>
42 // CHECK: %[[RR:.*]] = tensor.expand_shape %[[R]] {{\[}}[0, 1], [2]] : tensor<12544x16xf32> in…
43 // CHECK: return %[[RR]] : tensor<112x112x16xf32>

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