183       bool operator== (RegisterRef RR) const {  in operator ==()
184         return Reg == RR.Reg && Sub == RR.Sub;  in operator ==()
186       bool operator!= (RegisterRef RR) const { return !operator==(RR); }  in operator !=()
187       bool operator< (RegisterRef RR) const {  in operator <()
188         return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);  in operator <()
203     void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
236     bool isIntReg(RegisterRef RR, unsigned &BW);
295 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,  in addRefToMap()  argument
297   unsigned Mask = getMaskForSub(RR.Sub) | Exec;  in addRefToMap()
298   ReferenceMap::iterator F = Map.find(RR.Reg);  in addRefToMap()
300     Map.insert(std::make_pair(RR.Reg, Mask));  in addRefToMap()
305 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,  in isRefInMap()  argument
307   ReferenceMap::iterator F = Map.find(RR.Reg);  in isRefInMap()
310   unsigned Mask = getMaskForSub(RR.Sub) | Exec;  in isRefInMap()
769       RegisterRef RR = Op;  in getReachingDefForPred()  local
770       if (RR.Reg == PredR) {  in getReachingDefForPred()
774       if (RR.Reg != RD.Reg)  in getReachingDefForPred()
779       if (RR.Sub == RD.Sub)  in getReachingDefForPred()
781       if (RR.Sub == 0 || RD.Sub == 0)  in getReachingDefForPred()
803     RegisterRef RR = Op;  in canMoveOver()  local
807     if (!RR.Reg.isVirtual())  in canMoveOver()
810     if (isRefInMap(RR, Defs, Exec_Then))  in canMoveOver()
813     if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))  in canMoveOver()
1003       RegisterRef RR = Op;  in predicate()  local
1004       if (!RR.Reg.isVirtual())  in predicate()
1009         assert(RR.Sub && "Expecting a subregister on <def,read-undef>");  in predicate()
1013         RR.Sub = 0;  in predicate()
1015       addRefToMap(RR, Map, Exec);  in predicate()
1093 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {  in isIntReg()  argument
1094   if (!RR.Reg.isVirtual())  in isIntReg()
1096   const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);  in isIntReg()
1102     BW = (RR.Sub != 0) ? 32 : 64;  in isIntReg()