Lines Matching refs:RR
329 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth()
338 if (RR.Reg.isVirtual()) { in getRegBitWidth()
339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub); in getRegBitWidth()
342 assert(RR.Reg.isPhysical()); in getRegBitWidth()
344 (RR.Sub == 0) ? RR.Reg.asMCReg() : TRI.getSubReg(RR.Reg, RR.Sub); in getRegBitWidth()
348 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR, in getCell() argument
350 uint16_t BW = getRegBitWidth(RR); in getCell()
354 if (RR.Reg.isPhysical()) in getCell()
357 assert(RR.Reg.isVirtual()); in getCell()
360 const TargetRegisterClass *C = MRI.getRegClass(RR.Reg); in getCell()
364 CellMapType::const_iterator F = M.find(RR.Reg); in getCell()
366 if (!RR.Sub) in getCell()
368 BitMask M = mask(RR.Reg, RR.Sub); in getCell()
375 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC, in putCell() argument
380 if (!RR.Reg.isVirtual()) in putCell()
382 assert(RR.Sub == 0 && "Unexpected sub-register in definition"); in putCell()
384 M[RR.Reg] = RC.regify(RR.Reg); in putCell()
990 BT::RegisterCell BT::get(RegisterRef RR) const { in get()
991 return ME.getCell(RR, Map); in get()
994 void BT::put(RegisterRef RR, const RegisterCell &RC) { in put() argument
995 ME.putCell(RR, RC, Map); in put()