Home
last modified time | relevance | path

Searched refs:RMW (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Analysis/
H A DAliasAnalysis.cpp645 ModRefInfo AAResults::getModRefInfo(const AtomicRMWInst *RMW, in getModRefInfo() argument
648 return getModRefInfo(RMW, Loc, AAQIP); in getModRefInfo()
651 ModRefInfo AAResults::getModRefInfo(const AtomicRMWInst *RMW, in getModRefInfo() argument
655 if (isStrongerThanMonotonic(RMW->getOrdering())) in getModRefInfo()
659 AliasResult AR = alias(MemoryLocation::get(RMW), Loc, AAQI); in getModRefInfo()
/llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/
H A DMemProfiler.cpp348 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) { in isInterestingMemoryAccess() local
352 Access.AccessTy = RMW->getValOperand()->getType(); in isInterestingMemoryAccess()
353 Access.Addr = RMW->getPointerOperand(); in isInterestingMemoryAccess()
H A DHWAddressSanitizer.cpp753 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) { in getInterestingMemoryOperands() local
754 if (!ClInstrumentAtomics || ignoreAccess(I, RMW->getPointerOperand())) in getInterestingMemoryOperands()
756 Interesting.emplace_back(I, RMW->getPointerOperandIndex(), true, in getInterestingMemoryOperands()
757 RMW->getValOperand()->getType(), None); in getInterestingMemoryOperands()
779 if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) in getPointerOperandIndex() local
780 return RMW->getPointerOperandIndex(); in getPointerOperandIndex()
H A DAddressSanitizer.cpp1287 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) { in getInterestingMemoryOperands() local
1288 if (!ClInstrumentAtomics || ignoreAccess(I, RMW->getPointerOperand())) in getInterestingMemoryOperands()
1290 Interesting.emplace_back(I, RMW->getPointerOperandIndex(), true, in getInterestingMemoryOperands()
1291 RMW->getValOperand()->getType(), None); in getInterestingMemoryOperands()
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DAliasAnalysis.h778 ModRefInfo getModRefInfo(const AtomicRMWInst *RMW, const MemoryLocation &Loc);
781 ModRefInfo getModRefInfo(const AtomicRMWInst *RMW, const Value *P,
783 return getModRefInfo(RMW, MemoryLocation(P, Size));
917 ModRefInfo getModRefInfo(const AtomicRMWInst *RMW, const MemoryLocation &Loc,
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrAtomics.td634 // Truncating & zero-extending binary RMW patterns.
646 // Truncating & sign-extending binary RMW patterns.
649 // 64-bit) and select a zext RMW; the next instruction will be sext_inreg which
658 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
860 // Truncating & zero-extending ternary RMW patterns.
879 // Truncating & sign-extending ternary RMW patterns.
881 // zext RMW; the next instruction will be sext_inreg which is selected by
894 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DInferAddressSpaces.cpp469 else if (auto *RMW = dyn_cast<AtomicRMWInst>(&I)) in collectFlatAddressExpressions() local
470 PushPtrOperand(RMW->getPointerOperand()); in collectFlatAddressExpressions()
1002 if (auto *RMW = dyn_cast<AtomicRMWInst>(Inst)) in isSimplePointerUseValidToReplace() local
1004 (VolatileIsAllowed || !RMW->isVolatile()); in isSimplePointerUseValidToReplace()
H A DLoopStrengthReduce.cpp873 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Inst)) { in isAddressUse() local
874 if (RMW->getPointerOperand() == OperandVal) in isAddressUse()
892 } else if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Inst)) { in getAccessType() local
893 AccessTy.AddrSpace = RMW->getPointerAddressSpace(); in getAccessType()
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Datomic-mem-consistency.ll94 ; Out of several binary RMW instructions, here we test 'add' as an example.
142 ; Ternary RMW instruction: cmpxchg
H A Doffset-atomics.ll660 ; There are several RMW instructions, but here we only test 'add' as an example.
662 ; Basic RMW.
756 ; Basic RMW.
1077 ; Basic RMW.
1179 ; Basic RMW.
H A Datomic-rmw.ll4 ; Test atomic RMW (read-modify-write) instructions are assembled properly.
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp619 } else if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(UseInst)) { in collectUsesWithPtrTypes() local
620 if (RMW->isVolatile()) in collectUsesWithPtrTypes()
H A DSIISelLowering.cpp12721 unsigned AS = RMW->getPointerAddressSpace(); in shouldExpandAtomicRMWInIR()
12726 OptimizationRemarkEmitter ORE(RMW->getFunction()); in shouldExpandAtomicRMWInIR()
12730 auto MemScope = SSNs[RMW->getSyncScopeID()].empty() in shouldExpandAtomicRMWInIR()
12732 : SSNs[RMW->getSyncScopeID()]; in shouldExpandAtomicRMWInIR()
12736 << RMW->getOperationName(RMW->getOperation()) in shouldExpandAtomicRMWInIR()
12743 switch (RMW->getOperation()) { in shouldExpandAtomicRMWInIR()
12745 Type *Ty = RMW->getType(); in shouldExpandAtomicRMWInIR()
12764 if (RMW->getFunction() in shouldExpandAtomicRMWInIR()
12773 auto SSID = RMW->getSyncScopeID(); in shouldExpandAtomicRMWInIR()
12795 if (fpModeMatchesGlobalFPAtomicMode(RMW)) in shouldExpandAtomicRMWInIR()
[all …]
H A DAMDGPUISelLowering.cpp4808 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const { in shouldExpandAtomicRMWInIR()
4809 switch (RMW->getOperation()) { in shouldExpandAtomicRMWInIR()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleBtVer2.td183 // A folded store needs a cycle on the SAGU for the store data, most RMW
184 // instructions don't need an extra uop. ALU RMW operations don't seem to
H A DX86Schedule.td160 def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support.
H A DX86SchedSandyBridge.td1059 def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW
H A DX86ScheduleZnver3.td1444 defm : Zn3WriteResInt<WriteXCHG, [Zn3ALU0123], 0, [8], 2>; // Compare+Exchange - TODO RMW su…
H A DX86InstrArithmetic.td1237 // Patterns to recognize RMW ADC with loads in operand 1.
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp4912 if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(UserI)) { in FindAllMemoryUses() local
4915 MemoryUses.push_back({U.get(), RMW->getValOperand()->getType()}); in FindAllMemoryUses()
7961 if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(I)) { in optimizeInst() local
7962 unsigned AS = RMW->getPointerAddressSpace(); in optimizeInst()
7963 return optimizeMemoryInst(I, RMW->getPointerOperand(), in optimizeInst()
7964 RMW->getType(), AS); in optimizeInst()
H A DTargetLoweringBase.cpp2279 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) { in getAtomicMemOperandFlags() local
2280 if (RMW->isVolatile()) in getAtomicMemOperandFlags()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2088 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const { in shouldExpandAtomicRMWInIR() argument
2089 return RMW->isFloatingPointOperation() ? in shouldExpandAtomicRMWInIR()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td1809 // Read-Write-Modify (RMW) instructions.
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp4052 AtomicRMWInst *RMW = Builder.CreateAtomicRMW(llvm::AtomicRMWInst::Xchg, in EmitBuiltinExpr() local
4054 RMW->setVolatile(Volatile); in EmitBuiltinExpr()
4055 Result->addIncoming(RMW, BBs[i]); in EmitBuiltinExpr()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp18152 Function *RMW = Intrinsic::getDeclaration( in emitMaskedAtomicRMWIntrinsic() local
18160 Value *LoHi = Builder.CreateCall(RMW, {Addr, IncrLo, IncrHi}); in emitMaskedAtomicRMWIntrinsic()